@techreport{oai:ipsj.ixsq.nii.ac.jp:00214015,
 author = {李, 恒毅 and 岳, 学彬 and 孟, 林 and Hengyi, Li and Xuebin, Yue and Lin, Meng},
 issue = {6},
 month = {Nov},
 note = {The paper proposes a Sparsity-Gradient-Based layer-wise Pruning technique for compacting deep neural networks and accelerates the network by the Vitis AI on the Xilinx FPGA platform. The experimental results show that nearly 99.67% of parameters and 97.91% floating-point operations are pruned with only 1.2% accuracy decreased. With the support of Vitis AI, which offers a solution for adaptable and real-time AI inference acceleration, the pruned model is quantized and implemented on FPGA. The inference process achieves the throughput of 237.80 floating-point operations per second and running time of 4.21ms concerning VGG13BN, about 10 × speedup compared with the original model at single-thread mode. The paper also makes an in-depth analysis of the efficiency and utilization of the inference implementation, including the layer-wise workloads, running time, memory consumption, and so on. With the comprehensive analysis of the model deployed on FPGA, we plan to make further efforts to design the acceleration engine on hardware level by utilizing the potential of FPGA., The paper proposes a Sparsity-Gradient-Based layer-wise Pruning technique for compacting deep neural networks and accelerates the network by the Vitis AI on the Xilinx FPGA platform. The experimental results show that nearly 99.67% of parameters and 97.91% floating-point operations are pruned with only 1.2% accuracy decreased. With the support of Vitis AI, which offers a solution for adaptable and real-time AI inference acceleration, the pruned model is quantized and implemented on FPGA. The inference process achieves the throughput of 237.80 floating-point operations per second and running time of 4.21ms concerning VGG13BN, about 10 × speedup compared with the original model at single-thread mode. The paper also makes an in-depth analysis of the efficiency and utilization of the inference implementation, including the layer-wise workloads, running time, memory consumption, and so on. With the comprehensive analysis of the model deployed on FPGA, we plan to make further efforts to design the acceleration engine on hardware level by utilizing the potential of FPGA.},
 title = {Sparsity-Gradient を用いた深層学習モデルの圧縮とVitis-AI への実装},
 year = {2021}
}