{"updated":"2025-01-19T17:14:29.208449+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00213188","sets":["1164:1579:10482:10719"]},"path":["10719"],"owner":"44499","recid":"213188","title":["単一磁束量子回路によるビット幅可変加減算器の設計と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-10-04"},"_buckets":{"deposit":"8a344266-7fda-4f1c-82a2-3c836efedbc8"},"_deposit":{"id":"213188","pid":{"type":"depid","value":"213188","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"単一磁束量子回路によるビット幅可変加減算器の設計と評価","author_link":["545004","544999","545001","545006","544997","544998","545000","544996","545005","545002","545003"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"単一磁束量子回路によるビット幅可変加減算器の設計と評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"HW・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-10-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"九州大学／現在，株式会社ソシオネクスト"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"九州大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing 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hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体の微細化の限界が見え始め，新奇デバイスへの期待が高まっている．そのひとつに単一磁束量子（Single Flux Quantum: SFQ）回路がある．本研究では SFQ 回路と親和性の高いベクトルアーキテクチャに着目し，SFQ ベクトルプロセッサを実装することを目標としている．しかしながら，現状では SFQ 回路向けのベクトルアーキテクチャは提案されていない．そこで，近年主流の柔軟性を持ったベクトルプロセッサに必要な構成要素である，ビット幅可変加減算器の設計を行い，動作検証を行った．シミュレーションによる検証の結果，50GHz での正常動作が確認でき，SFQ 回路の高速性を維持しつつ，ビット幅可変加減算器が実現できることが確認できた．この回路はチップ試作を行っており，試作チップを用いた検証も行う予定である．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-10-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2021-ARC-246"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:14:05.693462+00:00","id":213188,"links":{}}