{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00212631","sets":["6164:6165:7651:10646"]},"path":["10646"],"owner":"44499","recid":"212631","title":["FPGA実装を指向した部分2値化オートエンコーダに基づく人型ロボットによる柔軟物操作システム"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-08-25"},"_buckets":{"deposit":"ec4c4aa0-9619-463d-9dc8-e8cef84833e1"},"_deposit":{"id":"212631","pid":{"type":"depid","value":"212631","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGA実装を指向した部分2値化オートエンコーダに基づく人型ロボットによる柔軟物操作システム","author_link":["542817","542815","542818","542816"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA実装を指向した部分2値化オートエンコーダに基づく人型ロボットによる柔軟物操作システム"},{"subitem_title":"Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高性能システム","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2021-08-25","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻"},{"subitem_text_value":"京都大学"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/212631/files/IPSJ-DAS2021016.pdf","label":"IPSJ-DAS2021016.pdf"},"date":[{"dateType":"Available","dateValue":"2023-08-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2021016.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e6c58f7f-d5ac-405e-9395-6741caa58809","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大原, 慧"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"粟野, 皓光"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Satoshi, Ohara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiromitsu, Awano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA 上に実装可能なニューラルネットワークを用いて人型ロボットで柔軟物を操作するシステムを提案する．柔軟物操作はロボットによる実現が困難なタスクとして知られているが，近年ニューラルネットワークを用いたシステムが実用化された．しかし，これらのシステムは GPU に依存しており，推論システムのロボット本体への組み込みは困難であった．そこで，性能を落とさずに FPGA に実装できるようネットワークの一部を 2 値化したオートエンコーダを提案する．Xilinx 社の ZCU102 上に実装した結果，3.1W の電力で 41.1FPS を達成し，Core i7 6700K と RTX 2080 Ti に実装したシステムと比較し，それぞれ 10 倍，3.7 倍の性能向上を実現した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A system for manipulating flexible objects with a humanoid robot using a neural network that can be implemented on an FPGA is proposed. Manipulating flexible objects is known to be a difficult task for robots, but recently, systems using neural networks have been put to practical use. However, these systems rely on GPUs, making it difficult to integrate the inference system into the robot itself. In this paper, we propose an auto-encoder where a part of the network is binarized so that it can be implemented on an FPGA without compromising the performance. We implemented the system on Xilinx ZCU102 and demonstrated 41.1FPS at 3.1W power, which is 10× and 3.7× better than the systems implemented on Core i7 6700K and RTX 2080 Ti, respectively.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"84","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2021論文集"}],"bibliographicPageStart":"78","bibliographicIssueDates":{"bibliographicIssueDate":"2021-08-25","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2021"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":212631,"updated":"2025-01-19T17:26:20.350695+00:00","links":{},"created":"2025-01-19T01:13:34.046383+00:00"}