{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00212623","sets":["6164:6165:7651:10646"]},"path":["10646"],"owner":"44499","recid":"212623","title":["汎用高位合成系をバックエンドとするRISC-V機械語からのバイナリ合成"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-08-25"},"_buckets":{"deposit":"fbb776d1-aaf2-4e6f-a7ec-480fb96ff469"},"_deposit":{"id":"212623","pid":{"type":"depid","value":"212623","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"汎用高位合成系をバックエンドとするRISC-V機械語からのバイナリ合成","author_link":["542775","542777","542776","542780","542778","542779"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"汎用高位合成系をバックエンドとするRISC-V機械語からのバイナリ合成"},{"subitem_title":"Binary Synthesis from RISC-V Executable Code Using General-Purpose High-Level Synthesizer","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成・プロセッサ設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2021-08-25","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"関西学院大学大学院理工学研究科"},{"subitem_text_value":"関西学院大学工学部"},{"subitem_text_value":"関西学院大学大学院理工学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Kwansei Gakuin Univ.","subitem_text_language":"en"},{"subitem_text_value":"School of Engineering, Kwansei Gakuin Univ.","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Kwansei Gakuin Univ.","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/212623/files/IPSJ-DAS2021008.pdf","label":"IPSJ-DAS2021008.pdf"},"date":[{"dateType":"Available","dateValue":"2023-08-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2021008.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6f58ce9c-8ceb-435e-bc80-8232e843d464","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中道, 凌"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石浦, 菜岐佐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"近藤, 匠"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryo, Nakamichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nagisa, Ishiura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takumi, Kondo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，バイナリ合成系の容易な実装手法として汎用の高位合成システムをバックエンドとして利用する方法を提案し，これに基づいて RISC-V 機械語からのバイナリ合成系を実装する．本手法ではリンク済みの機械語プログラムを入力として与え，これを実行する CPU と機能等価なハードウェアの設計記述を合成する．この際，機械語プログラムから CDFG (control data flow graph) ではなく高位合成可能な C プログラムを生成し，これを高位合成システムの入力としてハードウェアの設計記述を合成する．提案手法に基づいて RISC-V の RV32IM 命令セットを対象とするバイナリ合成系を実装した結果，C プログラムを高位合成したものと比べ回路規模は 1.04-3.75 倍に増加するものの，実行サイクル数とクリティカルパス遅延はほとんど同等のハードウェアを合成することができた．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This artcle proposes a facile way to implement binary synthesizers which utilize existing high-level synthesizers as their backends, and demonstrates its application to implement a binary synthesizer for the RISC-V instruction set. We assume a type of binary synthesizers which take a linked executable binary code as input and generate a design description of hardware which is functionally exquivalent to a CPU running the code. In our method, a C program in place of a CDFG (control dataflow graph) is generated from a binary code, which is fed into existing high-level synthesizers to produce a hardware design. In an experiment using a commercial high-level synthesizer, the execution cycles and critical path delay of the circuits, generated by our binary synthesizer from RV32IM binaries compiled from C codes, are almost the same as those of the circuits generated by the high-level synthesizer from the C codes, though the circuit size is 1.04 to 3.73 times larger.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"45","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2021論文集"}],"bibliographicPageStart":"39","bibliographicIssueDates":{"bibliographicIssueDate":"2021-08-25","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2021"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":212623,"updated":"2025-01-19T17:26:30.203043+00:00","links":{},"created":"2025-01-19T01:13:33.589686+00:00"}