{"id":212622,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00212622","sets":["6164:6165:7651:10646"]},"path":["10646"],"owner":"44499","recid":"212622","title":["BDDに基づく光論理回路における双対端子を利用した面積と電力の削減手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-08-25"},"_buckets":{"deposit":"34fe84c5-dee0-451f-bf7b-93d97f4ae7fa"},"_deposit":{"id":"212622","pid":{"type":"depid","value":"212622","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"BDDに基づく光論理回路における双対端子を利用した面積と電力の削減手法","author_link":["542773","542774"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"BDDに基づく光論理回路における双対端子を利用した面積と電力の削減手法"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"低電力・低エネルギー設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2021-08-25","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/212622/files/IPSJ-DAS2021007.pdf","label":"IPSJ-DAS2021007.pdf"},"date":[{"dateType":"Available","dateValue":"2023-08-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2021007.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"b20b8b52-0217-4a34-91a4-6158587f6cff","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"松尾, 亮祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"湊, 真一"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"集積ナノフォトニクスに基づく光論理回路は非常に高速な動作を実現することができるために近年注目を集めている．光の高速性を活かした論理合成手法として BDD に基づく手法が注目されているが，回路中に多数存在するスプリッタが原因で消費電力が非常に大きくなる課題がある．BDD に基づく光論理回路では双対な入力端子が余っている．この端子を活用してスプリッタを削減する手法を提案する．提案手法により，回路の遅延を増加させることなく，面積を削減しながら消費電力を大幅に削減できることを示す．ISCAS'85 ベンチマーク回路に LUT ベースの FPGA テクノロジーマッパーを適用して得られる 10 入力関数を用いた実験を行い，提案手法によりベストケースでは消費電力が 2 桁程度削減されることを示す．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"38","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2021論文集"}],"bibliographicPageStart":"32","bibliographicIssueDates":{"bibliographicIssueDate":"2021-08-25","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2021"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T17:26:31.248670+00:00","created":"2025-01-19T01:13:33.532993+00:00","links":{}}