{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00211918","sets":["1164:1579:10482:10619"]},"path":["10619"],"owner":"44499","recid":"211918","title":["Neural ODEの軽量化モデルによる小規模FPGA向けドメイン適応"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-07-13"},"_buckets":{"deposit":"70fb6daa-0363-4b5b-bdc3-7f5d238fa92c"},"_deposit":{"id":"211918","pid":{"type":"depid","value":"211918","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Neural ODEの軽量化モデルによる小規模FPGA向けドメイン適応","author_link":["539414","539415","539409","539412","539413","539411","539408","539410"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Neural ODEの軽量化モデルによる小規模FPGA向けドメイン適応"},{"subitem_title":"A Domain Adaptation Method using Light-Weight Neural ODE for Low-Cost FPGAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ニューラルネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-07-13","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科 "}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/211918/files/IPSJ-ARC21245020.pdf","label":"IPSJ-ARC21245020.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21245020.pdf","filesize":[{"value":"2.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"92a530cc-9e6c-4dca-a583-43d3bf5a6010","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川上, 大輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡邉, 寛悠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"杉浦, 圭祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 宏紀"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroki, Kawakami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hirohisa, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Keisuke, Sugiura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroki, Matsutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"エッジデバイスには計算リソースの制限があり，大規模なニューラルネットワークを用いることが難しい．深層学習の課題としてデータ領域の変化があり，これに適応させるドメイン適応という技術がある．これらの課題に 取り組んだ研究として，Neural ODE を用いたエッジデバイス向けドメイン適応手法が提案されている．しかし，その研究では深層学習モデルの積層構造を 1 つのみエッジデバイスとして FPGA（Field-Programmable Gate Array） にオフロードしており，他の積層構造をプロセッシングシステムで処理するため高速化が限られている．本研究では エッジデバイスとして小規模 FPGA を用いることを前提とした軽量化モデルを提案し，FPGA 上に全ての積層構造を実装しリソース使用量や精度の評価を行った．提案モデルを FPGA に載せることにより，一部の処理が 27.9 倍の高速化となることを示した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-07-13","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"20","bibliographicVolumeNumber":"2021-ARC-245"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T17:37:58.113171+00:00","created":"2025-01-19T01:13:02.135769+00:00","id":211918}