{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00211904","sets":["1164:1579:10482:10619"]},"path":["10619"],"owner":"44499","recid":"211904","title":["マルチレベルセル相変化メモリを用いた連想メモリ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-07-13"},"_buckets":{"deposit":"b87a0771-c7c7-4945-ae68-a0ba4e451d37"},"_deposit":{"id":"211904","pid":{"type":"depid","value":"211904","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"マルチレベルセル相変化メモリを用いた連想メモリ","author_link":["539346","539349","539348","539347"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチレベルセル相変化メモリを用いた連想メモリ"},{"subitem_title":"Content addressable memory using multi-level cell phase-change memory","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"マイクロアーキテクチャ・デバイス技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-07-13","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"千葉大学大学院融合理工学府"},{"subitem_text_value":"千葉大学大学院工学研究院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Chiba University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/211904/files/IPSJ-ARC21245006.pdf","label":"IPSJ-ARC21245006.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21245006.pdf","filesize":[{"value":"2.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"38e79dd0-b210-4380-a2dc-6c927a3f4256","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高橋, 知宏"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"難波, 一輝"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomohiro, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuteru, Namba","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現在，連想メモリのメモリセルには，SRAM が用いられることが一般的であるが，SRAM を用いると必要なトランジスタ数が多くなるという欠点が存在する．このため，SRAM よりは動作速度が遅くなるが，トランジスタ数は少なくなる様々な素子を使うことが提案されている．それらの素子の 1 つに相変化メモリがあり，先行研究では，シングルレベルセル相変化メモリを連想メモリセルへ用いていた．そして，相変化メモリはマルチレベルセルでも運用可能という特徴を持つ．そこで本研究では，相変化メモリを用いて，連想メモリセルをマルチレベルセルで運用するための回路を考案し，それを HSPICE でシミュレーションしてその動作を検証した．結果，連想メモリの実装に必要なトランジスタ数を，1bit 当たり 9~10 個から 6 個にまで削減することに成功した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Nowadays, SRAM is generally used for memory cells of a content addressable memory. However, using SRAM has the disadvantage of increasing the number of transistors. For this reason, various elements have been proposed to reduce the number of transistors. A phase-change memory (PCM) is one of the promising elements. In the previous researches, the phase-change memory was operated as a single-level memory system in a content addressable memory. And the phase-change memory can operate as a multi-level memory system. Therefore, this work has presented a content addressable memory cell using a multi-level cell phase-change memory, and simulated it with HSPICE to verify its operation. As a result, we succeeded in reducing the number of transistors from 9~10 to 6 per 1bit.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-07-13","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2021-ARC-245"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":211904,"updated":"2025-01-19T17:38:16.093116+00:00","links":{},"created":"2025-01-19T01:13:01.331100+00:00"}