{"updated":"2025-01-19T17:56:01.356633+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00211036","sets":["1164:4088:10494:10571"]},"path":["10571"],"owner":"44499","recid":"211036","title":["FPGAによるソフトウェア解析環境「Iana」の提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-05-06"},"_buckets":{"deposit":"8db7b62b-3c6a-4a1f-a228-66cd0c5329b3"},"_deposit":{"id":"211036","pid":{"type":"depid","value":"211036","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGAによるソフトウェア解析環境「Iana」の提案","author_link":["535505","535506","535503","535507","535504","535508"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAによるソフトウェア解析環境「Iana」の提案"},{"subitem_title":"FPGA-based Software Analyzer: a Design Proposal","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"CSEC","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-05-06","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"国立研究開発法人情報通信研究機構"},{"subitem_text_value":"国立研究開発法人情報通信研究機構"},{"subitem_text_value":"国立研究開発法人情報通信研究機構／大阪大学大学院工学研究科"},{"subitem_text_value":"国立研究開発法人情報通信研究機構"},{"subitem_text_value":"国立研究開発法人情報通信研究機構"},{"subitem_text_value":"国立研究開発法人情報通信研究機構"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"National Institute of Information and Communications Technology","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Information and Communications Technology","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Information and Communications Technology / Graduate School of Engineering, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Information and Communications Technology","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Information and Communications Technology","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Information and Communications Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/211036/files/IPSJ-IOT21053014.pdf","label":"IPSJ-IOT21053014.pdf"},"date":[{"dateType":"Available","dateValue":"2023-05-06"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-IOT21053014.pdf","filesize":[{"value":"321.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"43"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1ad3194b-53b2-4c06-8dab-b04dd894ce1a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"金谷, 延幸"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津田, 侑"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高野, 祐輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤原, 吉唯"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"伊沢, 亮一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 大介"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12326962","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8787","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"組み込み機器開発では，実機やソフトウェアエミュレーションなど，テストやデバッグなどの内容に応じ複数の実装形態を使い分ける．各実装形態には一長一短があり，実機では解析手段が限られるため不具合発生時の状態が把握できない場合があり，エミュレーションでは詳細に追跡したくてもその不具合が再現せず追跡できない場合がある．そこで我々は，複数の実現環境における CPU の任意時点における状態を再現し，相互にマイグレーション可能なソフトウェア解析環境 Iana（アイアナ）を提案する．Ianaの特徴は CPU やメモリ，I/O の状態をすべて記録し，任意時点の状態と挙動を再現・変更可能な解析専用 CPU にあり，本稿では CPU を FPGA にて実装した．さらに，任意時点での実行状態を QEMU や評価ボードに書き戻し，デバッギング機能とともに解析を再開することができる．Iana を用いることで，解析対象における重要なイベントの絞り込みを行い，またその前の状態に遡ることが可能であり，組み込み機器や IoT 機器などのファームウェア解析にて適切な手段の選択が可能となる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Embedded-software developers choose real embedded devices or software emulation as a debugging platform for their developing programs, depending on their purpose of debugging at the time. This is because those platforms have both advantages and drawbacks (e.g., real devices basically do not possess good debugging functionality and a software emulator could cause some semantic gaps between a real device and emulation). To fully leverage advantages of every platform, this paper presents Iana, a system featuring a CPU implemented on FPGA for migrating execution-state of software from a debugging platform of FPGA to another (QEMU or a real embedded device) and vise versa. The execution-state includes CPU registers, memory, and I/O. As a usage example of Iana, developers debug their programs on a real device until a bug is found, and then they continue the debugging on FPGA with better debugging functionality after the migration. Namely, Iana enables developers to select any execution-state in migration (e.g., the execution-state after 500 instructions executed from the beginning). This is achieved by tracing all executed instructions of software. The experiments in this paper using two software samples confirm that a prototype of Iana correctly migrated execution-states from a RISC-V implemented on FPGA to QEMU and a real RISC-V.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告インターネットと運用技術（IOT）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-05-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"14","bibliographicVolumeNumber":"2021-IOT-53"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:12:13.885145+00:00","id":211036,"links":{}}