{"created":"2025-01-19T01:11:42.140252+00:00","updated":"2025-01-19T18:08:45.225807+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210483","sets":["1164:1579:10482:10561"]},"path":["10561"],"owner":"44499","recid":"210483","title":["レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"ef8659dd-9325-46c0-8f32-c30b55eefc42"},"_deposit":{"id":"210483","pid":{"type":"depid","value":"210483","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法","author_link":["533001","533002","533003","532998","533000","532999"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法"},{"subitem_title":"A Logic Locking Method Based on Anti-SAT at Register Transfer Level","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高信頼化技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本大学"},{"subitem_text_value":"日本大学"},{"subitem_text_value":"京都産業大学情報理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nihon University","subitem_text_language":"en"},{"subitem_text_value":"Nihon University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Engineering,Kyoto Sangyo University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210483/files/IPSJ-ARC21244034.pdf","label":"IPSJ-ARC21244034.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21244034.pdf","filesize":[{"value":"2.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"5ebb720c-a521-4b68-93e5-c820e35eaec5","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"辻川, 敦也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"細川, 利典"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉村, 正義"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Atsuya, Tsujikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Hosokawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Yoshimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，大規模化に伴い VLSI を設計会社 1 社のみで設計を行うのが困難になり，IP ベンダより IP コアを購入し必要な部分のみを設計する手法を用いている．一方，IP コアは著作権侵害を容易に行えるという欠点を持つため，論理暗号化を施す必要がある．しかしながら，従来の論理暗号化手法は，SAT 攻撃によって正しい鍵を容易に解読される．SAT 攻撃に耐性のあるアンチ SAT に基づく論理暗号化法が提案されているが，その方法をゲートレベルの論理回路に設計することは困難である．それゆえ，本論文では，レジスタ転送レベルにおいてアンチ SAT に基づく論理暗号化手法を提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. However, with conventional logic locking methods, the correct key can be easily decrypted by a SAT attack. Therefore, anti-SAT methods, which are logic locking method that is resistant to SAT attacks, have been proposed. However, it is difficult to design logic locking based on anti-SAT into logic circuits at gate level. In this paper, we propose a logic locking method based on anti-SAT at register transfer level.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"34","bibliographicVolumeNumber":"2021-ARC-244"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":210483,"links":{}}