{"created":"2025-01-19T01:11:41.805827+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210477","sets":["1164:1579:10482:10561"]},"path":["10561"],"owner":"44499","recid":"210477","title":["パケット集約/分割ルータのFPGAによる試作"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"08794949-aa7b-4a32-8e4b-d203064911dd"},"_deposit":{"id":"210477","pid":{"type":"depid","value":"210477","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"パケット集約/分割ルータのFPGAによる試作","author_link":["532960","532959","532956","532958","532957","532961"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"パケット集約/分割ルータのFPGAによる試作"},{"subitem_title":"Prototyping of A Packet Aggregation/Disaggregation Router with FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"愛知工業大学工学部"},{"subitem_text_value":"愛知工業大学工学部"},{"subitem_text_value":"愛知工業大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Aichi Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Aichi Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Aichi Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210477/files/IPSJ-ARC21244028.pdf","label":"IPSJ-ARC21244028.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21244028.pdf","filesize":[{"value":"2.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"286a8139-96eb-4114-ae27-a1ffef0f2765","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高山, 史朗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤枝, 直輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"青木, 道宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shiro, Takayama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoki, Fujieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Michihiro, Aoki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"IoT サービスの浸透によりネットワークのトラフィック量が増加している．とりわけ，サイズが極めて小さいパケットの増加は，ルータのパケット処理性能に悪影響を及ぼす．ネットワーク上のパケット数を削減する方法の 1 つに，大量の被集約パケットを 1 つの集約パケットとして再構築するパケット集約が挙げられる．本稿では，FPGA 制御可能なネットワークハードウェア開発プラットフォームであるNetFPGA を用いて，パケット集約/分割ルータのハードウェアによる試作を行った結果について報告する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Network traffic volume is increasing due to the growth of IoT services. In particular, increase of short packets may affect the packet processing performance of routers. One of the methods to reduce the number of packets on the network is called packet aggregation, where a router reconstructs many short packets into an aggregated packet, and vice versa. In this article, we report the results of our hardware prototyping of packet aggregation/disaggregation router using NetFPGA, a platform for network hardware development that includes an FPGA.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"28","bibliographicVolumeNumber":"2021-ARC-244"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":210477,"updated":"2025-01-19T18:08:51.942985+00:00","links":{}}