{"created":"2025-01-19T01:11:41.750306+00:00","updated":"2025-01-19T18:08:53.157437+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210476","sets":["1164:1579:10482:10561"]},"path":["10561"],"owner":"44499","recid":"210476","title":["メモリネットワークを用いたコヒーレンスディレクトリの最適配置"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"6c19d38d-de0d-43a5-99eb-b115ea93addf"},"_deposit":{"id":"210476","pid":{"type":"depid","value":"210476","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"メモリネットワークを用いたコヒーレンスディレクトリの最適配置","author_link":["532946","532947","532949","532951","532955","532953","532950","532948","532954","532952"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メモリネットワークを用いたコヒーレンスディレクトリの最適配置"},{"subitem_title":"Optimal placement of coherence directories using memory networks","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"National Institute of InforrnaticsHitotsubashi","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210476/files/IPSJ-ARC21244027.pdf","label":"IPSJ-ARC21244027.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21244027.pdf","filesize":[{"value":"1.4 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英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuki, Kameyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshiya, Shikama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoya, Niwa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Michihiro, Koibuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":" Hybrid Memory Cube (HMC) は，DRAM チップを三次元積層し，最下層にロジック層を配置して管理するメモリモジュールである．ロジック層はルーティング機能を有しており，パケットを目的地までルーティングでき る．そこで，複数の HMC を相互接続することでメモリネットワークを構築することが可能である．従来のメモリネットワークでは，データコヒーレンスを管理するコヒーレンスディレクトリはプロセッサが管理すると想定されていた．しかし，プロセッサにコヒーレンスディレクトリを配置すると，プロセッサから見て自身が管理していない HMC に対してメモリアクセスを行う際に，それを管理するプロセッサのコヒーレンスディレクトリを参照することが必要で ある．そのため，DRAM の容量が大きくなった際にその消費エネルギーが大きくなってしまい，スケーラビリティが制限される．本研究ではコヒーレンスディレクトリを HMC のロジック層に配置し，HMC が各自のデータのコヒー レンスを管理する方法を提案する．これによって，消費エネルギーの削減や，スケーラビリティの確保が可能である．メモリ参照に必要な平均ホップ数を，コヒーレンスディレクトリをプロセッサに配置した場合と HMC のロジック層に配置した場合で比較した．その結果，コヒーレンスディレクトリを HMC のロジック層に配置した場合は，プロセッサにコヒーレンスディレクトリを配置した際に，他のプロセッサが管理する HMC に対してメモリアクセスを行った場合に比べて約 7.2 ％消費エネルギーを削減可能であることが分かった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"27","bibliographicVolumeNumber":"2021-ARC-244"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":210476,"links":{}}