{"updated":"2025-01-19T18:09:28.537910+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210451","sets":["1164:1579:10482:10561"]},"path":["10561"],"owner":"44499","recid":"210451","title":["整合性ツリーおよび暗号化機構を持つ不揮発性メインメモリエミュレータの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"cc99ef92-1fa6-4ba8-a02f-6fc18d0b78e8"},"_deposit":{"id":"210451","pid":{"type":"depid","value":"210451","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"整合性ツリーおよび暗号化機構を持つ不揮発性メインメモリエミュレータの実装","author_link":["532804","532806","532805"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"整合性ツリーおよび暗号化機構を持つ不揮発性メインメモリエミュレータの実装"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学基幹理工学研究科"},{"subitem_text_value":"早稲田大学基幹理工学研究科"},{"subitem_text_value":"早稲田大学基幹理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Fundamental Science and Engeneering, Waseda Univ","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engeneering, Waseda Univ","subitem_text_language":"en"},{"subitem_text_value":"School of Fundamental Science and Engeneering, Waseda Univ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210451/files/IPSJ-ARC21244002.pdf","label":"IPSJ-ARC21244002.pdf"},"date":[{"dateType":"Available","dateValue":"2023-03-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21244002.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9860e243-f899-479a-8d1e-f4ac3495cb3a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"林, 知輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"大森, 侑"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"木村, 啓二"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"IoT デバイス等に近接して高速かつ低遅延な処理ができるエッジコンピューティングに注目が集まっている．エッジコンピューティングで機密性の高い計算を行う場合，盗聴・改竄から保護しなければならない．その方法として信頼実行環境（Trusted Execution Environment: TEE）が注目されている．既存の TEE では補助記憶の利用に制限があるが，TEE から不揮発性メインメモリ（Non-Volatile Main Memory: NVMM）を利用することで，複雑なデバイスドライバを経由することなく簡便にデータを保存可能となる．さらに，NVMM に暗号化や情報の整合性保証を行う機構を設けることにより NVMM 上のデータが保護できる．しかしながら，このようなシステムを評価できる環境が現在不足している．そこで本稿では，整合性ツリーと暗号で保護された NVMM のエミュレータを提案する．CPU と FPGA を搭載したボードである Zynq-7000 SoC ZC706 上に本エミュレータを実装し，FPGA 上に実装されたメモリ保護機構は 50[MHz] で動作することを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"2021-ARC-244"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:11:40.348907+00:00","id":210451,"links":{}}