{"created":"2025-01-19T01:11:39.569680+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210437","sets":["1164:2036:10484:10562"]},"path":["10562"],"owner":"44499","recid":"210437","title":["ソフトプロセッサの相互検証に関するケーススタディ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"e4d8100b-f542-4748-b7c4-ec4ef8fffe31"},"_deposit":{"id":"210437","pid":{"type":"depid","value":"210437","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"ソフトプロセッサの相互検証に関するケーススタディ","author_link":["532748","532750","532747","532749"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ソフトプロセッサの相互検証に関するケーススタディ"},{"subitem_title":"A case study on cross-verification of soft processor","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"愛知工業大学"},{"subitem_text_value":"愛知工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Aichi Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Aichi Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210437/files/IPSJ-SLDM21194037.pdf","label":"IPSJ-SLDM21194037.pdf"},"date":[{"dateType":"Available","dateValue":"2023-03-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21194037.pdf","filesize":[{"value":"270.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d63338a1-35b9-4175-b321-da22257ea4c1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"松川, 達哉"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤枝, 直輝"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tatsuya, Matsukawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoki, Fujieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ソフトプロセッサの検証では，しばしばプロセッサシミュレータとソフトプロセッサとの間で命令実行結果を比較することが行われる．システムコールを含み，ファイルなどを扱う実用的なアプリケーションに対しては，シミュレータではシステムコールを模倣する対応法があるが，この方法をソフトプロセッサに適用するのは困難であった．本稿では，SystemVerilog を C/C++ 言語に変換する Verilator というツールを用いて，こうしたアプリケーションを用いたソフトプロセッサの検証を容易に行う手法を提案する．また，本手法を RISC-V ソフトプロセッサである kronos の検証に適用したケーススタディについて述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Verification of a soft processor is often conducted by comparing results of instruction execution between a processor simulator and a soft processor. To simulate a practical application that includes system call, a simulator can emulate the execution of system call; however, it is difficult for a soft processor to adopt this approach. In this paper, we propose a method to apply system call emulation easily to a soft processor using Verilator, which converts SystemVerilog to C/C++ language. We also present a case study where the proposed method is applied to Kronos, a RISC-V soft processor.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"37","bibliographicVolumeNumber":"2021-SLDM-194"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":210437,"updated":"2025-01-19T18:09:46.675173+00:00","links":{}}