{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210405","sets":["1164:2036:10484:10562"]},"path":["10562"],"owner":"44499","recid":"210405","title":["オイラー動画像誇張処理を対象としたCPU-FPGAハイブリッドシステムの実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-18"},"_buckets":{"deposit":"d8522589-b6fe-4350-ac07-46cf1eab72a4"},"_deposit":{"id":"210405","pid":{"type":"depid","value":"210405","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"オイラー動画像誇張処理を対象としたCPU-FPGAハイブリッドシステムの実装と評価","author_link":["532563","532565","532559","532558","532561","532560","532564","532562"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"オイラー動画像誇張処理を対象としたCPU-FPGAハイブリッドシステムの実装と評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"組み込みシステムとFPGA","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-03-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"株式会社フィックスターズ"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"Fixstars Solutions Inc."},{"subitem_text_value":"九州大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fixstars Solutions Inc.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210405/files/IPSJ-SLDM21194005.pdf","label":"IPSJ-SLDM21194005.pdf"},"date":[{"dateType":"Available","dateValue":"2023-03-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21194005.pdf","filesize":[{"value":"735.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8f0cc71b-ec34-4b30-ab30-bb9468a878bb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"上野, 麟"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"谷本, 輝夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"後藤, 孝行"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"丸岡, 晃"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川上, 哲志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小野, 貴継"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 拓郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 弘士"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"オイラー動画像誇張処理 (EVM) は動画像における見えの微小な変化を数値計算により増幅し誇張することでそれらの検出を容易にするアプリケーションである．本研究では，組み込み機器における EVM のリアルタイム実行の実現を目指しており，そのため CPU-FPGA ハイブリッドシステムとしての設計及び実装に取り組んでいる．本稿では，CPU-FPGA システムの基本実装（ベースライン）からボトルネックとなる FPGA オフロード部分を抽出し，これに対して，1) CPU-FPGA 間のデータ転送性能の向上，2) FPGA 処理における演算並列度の改善，を検討する．そして，3) 当該オフロード部分の実装に基づく性能電力モデルを構築し，改善方式の効果を評価する．評価結果に基づくモデリングの結果，全ての IP コアへ本改善手法を適用できれば電力投資効果の観点から GPU 利用に対し 1.129 倍の性能向上を達成できる可能性が明らかになった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2021-SLDM-194"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":210405,"updated":"2025-01-19T18:10:27.623712+00:00","links":{},"created":"2025-01-19T01:11:37.785864+00:00"}