{"id":210318,"updated":"2025-01-19T18:11:57.191404+00:00","links":{},"created":"2025-01-19T01:11:32.947058+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00210318","sets":["6164:6165:9654:10560"]},"path":["10560"],"owner":"44499","recid":"210318","title":["Multirate Model Parallelization for MPSoC with FPGA in Model-Based Development: A Case Study"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-15"},"_buckets":{"deposit":"c870cedc-2b51-4fec-b895-2de331fee50c"},"_deposit":{"id":"210318","pid":{"type":"depid","value":"210318","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Multirate Model Parallelization for MPSoC with FPGA in Model-Based Development: A Case Study","author_link":["532122","532126","532124","532125","532123","532127","532121","532128","532129","532119","532118","532120"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Multirate Model Parallelization for MPSoC with FPGA in Model-Based Development: A Case Study"},{"subitem_title":"Multirate Model Parallelization for MPSoC with FPGA in Model-Based Development: A Case Study","subitem_title_language":"en"}]},"item_type_id":"18","publish_date":"2021-03-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"Nagoya University"},{"subitem_text_value":"NEC Solution Innovators, Ltd."},{"subitem_text_value":"Nanzan University"},{"subitem_text_value":"Nagoya University"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"NEC Solution Innovators, Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Nanzan University","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/210318/files/IPSJ-APRIS2020002.pdf","label":"IPSJ-APRIS2020002.pdf"},"date":[{"dateType":"Available","dateValue":"2021-03-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-APRIS2020002.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"62840234-5e8d-477c-9b50-9f0dd06e66ef","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryota, Yamamoto"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masataka, Ogawa"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Oinuma"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaki, Kondo"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Honda"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masato, Edahiro"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryota, Yamamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masataka, Ogawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Oinuma","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaki, Kondo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Honda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masato, Edahiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper presents an integrated development environment, HS-MBP, to generate parallelized code and executables for MPSoC with FPGA, named Field-Programmable Heterogeneous SoC (FP-HSoC), in model-based development. In our environment, we propose an automatic code generation for communication mechanism between sub-models with different control periods. Using this mechanism, our environment is capable of executable generation from multirate models, which are hard to design when multirate systems like robot IoT are constructed on FP-HSoC. Our environment has been applied to an multirate model as a case study. The results show that HS-MBP successfully generated parallelized codes of multirate systems for several patterns of block assignment to FP-HSoC. With the results of the case study, we discuss workflow for model-based parallelization of multirate models on FP-HSoC and future work.","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents an integrated development environment, HS-MBP, to generate parallelized code and executables for MPSoC with FPGA, named Field-Programmable Heterogeneous SoC (FP-HSoC), in model-based development. In our environment, we propose an automatic code generation for communication mechanism between sub-models with different control periods. Using this mechanism, our environment is capable of executable generation from multirate models, which are hard to design when multirate systems like robot IoT are constructed on FP-HSoC. Our environment has been applied to an multirate model as a case study. The results show that HS-MBP successfully generated parallelized codes of multirate systems for several patterns of block assignment to FP-HSoC. With the results of the case study, we discuss workflow for model-based parallelization of multirate models on FP-HSoC and future work.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"13","bibliographic_titles":[{"bibliographic_title":"Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform"}],"bibliographicPageStart":"6","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-15","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2020"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}