{"id":209294,"updated":"2025-01-19T18:33:49.423535+00:00","links":{},"created":"2025-01-19T01:10:36.851920+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00209294","sets":["1164:2036:10484:10485"]},"path":["10485"],"owner":"44499","recid":"209294","title":["FPGA向き自己同期型パイプライン回路構成法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-01-18"},"_buckets":{"deposit":"6ff558a8-befa-4ed3-9e78-3df8261a5c9e"},"_deposit":{"id":"209294","pid":{"type":"depid","value":"209294","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGA向き自己同期型パイプライン回路構成法","author_link":["527248","527247","527246","527245","527249"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA向き自己同期型パイプライン回路構成法"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-01-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大学"},{"subitem_text_value":"筑波大学"},{"subitem_text_value":"高知工科大学"},{"subitem_text_value":"筑波大学"},{"subitem_text_value":"筑波大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/209294/files/IPSJ-SLDM21193025.pdf","label":"IPSJ-SLDM21193025.pdf"},"date":[{"dateType":"Available","dateValue":"2023-01-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21193025.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4162c61b-b567-43cf-bdad-9b13b451cddd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉川, 千里"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三宮, 秀次"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岩田, 誠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐藤, 聡"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西川, 博昭"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"自己同期型パイプラインは，データ処理中のパイプライン段のみが駆動される省電力動作を自然に実現でき，高い性能対消費電力効率が求められるシステムの実現に有望な回路アーキテクチャである．システム開発の要となるプロトタイピングには，柔軟な試作を可能とし，最終生産物にもなり得る商用 FPGA の活用が望ましい．しかし，FPGA とその CAD ツールは同期回路の実装を指向しているため，非同期回路の一種である自己同期型パイプラインは，標準的な回路構成と設計手順では，FPGA 上に実装できなかった．本稿は，Xilinx 社と Intel 社のそれぞれの FPGA を対象に，FPGA の構成要素である LUT を活用した小規模な自己同期型転送制御回路と，それに基づく自己同期型パイプラインの FPGA 実装を可能とする設計手順からなる回路構成法を提案する．実装結果に基づき，提案回路は従来に比べて 50% の回路規模で実現でき，これにより，パイプラインのスループットを最大で約 3.2 倍に向上できることに加え，応用例の一つであるプロセッサのスループットを最大で約 1.6 倍に向上できることを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-01-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2021-SLDM-193"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}