{"id":209258,"updated":"2025-01-19T18:34:29.632599+00:00","links":{},"created":"2025-01-19T01:10:34.854978+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00209258","sets":["1164:1579:10482:10483"]},"path":["10483"],"owner":"44499","recid":"209258","title":["高位合成ツールCyberWorkBenchを用いたマルチFPGAボード設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-01-18"},"_buckets":{"deposit":"92687f14-2707-4b18-9cab-c94171953f2e"},"_deposit":{"id":"209258","pid":{"type":"depid","value":"209258","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"高位合成ツールCyberWorkBenchを用いたマルチFPGAボード設計","author_link":["527019","527014","527015","527017","527020","527016","527018","527021"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位合成ツールCyberWorkBenchを用いたマルチFPGAボード設計"},{"subitem_title":"A multi-FPGA system design environment with CyberWorkBench","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"分散システム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-01-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"日本電気株式会社"},{"subitem_text_value":"東京大学工学系研究科付属システムデザイン研究センター"},{"subitem_text_value":"慶應義塾大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Information and Computer Science, Keio University","subitem_text_language":"en"},{"subitem_text_value":"NEC","subitem_text_language":"en"},{"subitem_text_value":"University of Tolyo System Design Lab.","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Information and Computer Science, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/209258/files/IPSJ-ARC21243022.pdf","label":"IPSJ-ARC21243022.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC21243022.pdf","filesize":[{"value":"2.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"49af76a0-af74-4944-8814-7f4b87df9df7","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鈴木, 裕章"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高橋, 渡"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"若林, 一敏"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, Suzuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Wataru, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazutoshi, Wakabayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"複数の FPGA ボードを直接高速シリアルリンクで接続したマルチ FPGA システムは，MEC (Multi-edge access Computing) 用の計算ノードとして注目されているが，Vivado-HLS などの既存の設計ツールは，複数の FPGA チップによる並列処理の設計にほとんど対応していない．そのため，現状マルチ FPGA ボードでアプリケーションを開発する場合に問題となるのは，マルチ FPGA ボードで行う処理の並列シミュレーションができない点である．本稿では，マルチ FPGA システム FiC (Flow-in-Cloud) を対象として，並列シミュレーション環境の構築を目指す．その第一歩として，CWB (CyberWorkBench) を利用して SystemC を用いて LeNet を実装し，並列シミュレーションを行った．評価として，C++ 及び SystemC で実装した場合の，画像 5 枚分の判定結果出力までの各シミュレーション動作時間を測定した．結果としては C++ の動作レベルシミュレーションで 0.28sec，SystemC 動作レベルシミュレーションで 28.73sec，SystemC サイクル精度シミュレーションで 797.10sec となった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-01-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22","bibliographicVolumeNumber":"2021-ARC-243"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}