{"updated":"2025-01-19T19:16:20.201269+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00206944","sets":["934:1119:10056:10286"]},"path":["10286"],"owner":"44499","recid":"206944","title":["HPCスイッチにおけるルーティングテーブルキャッシュの研究"],"pubdate":{"attribute_name":"公開日","attribute_value":"2020-09-17"},"_buckets":{"deposit":"5331beb4-ab15-4d04-b20e-0d651c6e2fd1"},"_deposit":{"id":"206944","pid":{"type":"depid","value":"206944","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"HPCスイッチにおけるルーティングテーブルキャッシュの研究","author_link":["515468","515472","515470","515473","515469","515471"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"HPCスイッチにおけるルーティングテーブルキャッシュの研究"},{"subitem_title":"A Study of Routing-table Cache on HPC Switches","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"スイッチアーキテクチャ，相互結合網，キャッシュ","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2020-09-17","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"国立情報学研究所／総合研究大学院大学"},{"subitem_text_value":"電気通信大学大学院"},{"subitem_text_value":"国立情報学研究所／総合研究大学院大学／国立研究開発法人科学技術振興機構，さきがけ"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"National Institute of Informatics / SOKENDAI","subitem_text_language":"en"},{"subitem_text_value":"The University of Electro-Communications","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Informatics / SOKENDAI / JST, PRESTO","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/206944/files/IPSJ-TACS1302002.pdf","label":"IPSJ-TACS1302002.pdf"},"date":[{"dateType":"Available","dateValue":"2022-09-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS1302002.pdf","filesize":[{"value":"2.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"377604ce-60ec-495a-abc2-f71120bac2db","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2020 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"平澤, 将一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"八巻, 隼人"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"鯉渕, 道紘"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shoichi, Hirasawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hayato, Yamaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Michihiro, Koibuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"HPC（High-Performance Computing）システムにおける並列アプリケーションの性能は，計算ノード間の相互結合網の通信遅延により影響を受ける．相互結合網においてパケットは複数のスイッチを経由して転送されるため，特にメッセージサイズが小さい場合に，スイッチ遅延が通信遅延の支配的要因である．典型的なスイッチでは，ルーティング処理がオフチップCAM（Content Addressable Memory）に基づくテーブルルックアップで実装されるため，大きな遅延が生じる．そこで，本研究ではHPCスイッチにルーティングテーブルキャッシュを適用した場合のスイッチ遅延の削減効果を示す．本HPCスイッチでは，各入力ポートにルーティングテーブルキャッシュを配置する．本キャッシュがヒットした場合，CAMアクセスを避けることができるため，スイッチ遅延を削減することが期待できる．キャッシュのシミュレーション結果より，4ウェイの連想数で2,048エントリのキャッシュを有するスイッチで構成された相互結合網において，512台の計算ノード間の通信に対する競合性ミスの発生は0.1%以下となることが分かった．また，SimGridシミュレーションの結果，256台のスイッチを用いた相互結合網において，ルーティングテーブルキャッシュの導入により，NAS並列ベンチマークの性能を平均6.9%向上させることに成功した．さらに，大規模な相互結合網の解析結果より，ジョブサイズが十分に大きい場合に生じる容量性キャッシュミスが与える通信遅延への影響は限定的であり，本キャッシュを導入することにより，無負荷通信遅延を13%から19%と大幅に削減できることが分かった．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Parallel applications become sensitive to communication latencies of interconnection networks between compute nodes on HPC (High-Performance Computing) systems. Switch delay dominates communication latencies in interconnection networks especially for short messages, because a packet is transferred to a destination via multiple intermediate switches. At a conventional switch, routing decision is based on off-chip CAM (Content Addressable Memory)-based table lookup, and it imposes a significant delay. In this study, we exploit the application of on-chip routing-table cache for HPC switches. We place routing-table cache at each input port on the switch. The routing-table cache can bypass the CAM table lookup when it hits, then significantly reducing the switch delay. Our cache simulation results show that a 4-way set associative cache with 2,048 entries has less than 0.1% of the conflict miss rate on 256-nodes interconnection networks. Our SimGrid simulation results show that the introduction of routing-table cache on each switch improves 6.9%, in average, of performance of NAS Parallel Benchmarks on 256-node interconnection networks. Our analysis results show that the impact of the capacity cache miss on the communication latency is negligible even if a job size becomes large. The routing-table cache efficiently reduces the zero-load communication latency by 13% to 19%.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"12","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2020-09-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"13"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:08:50.835347+00:00","id":206944,"links":{}}