{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00204975","sets":["6504","6504:10247","6504:10247:10257"]},"path":["6504","10247","10257"],"owner":"6748","recid":"204975","title":["分散深層学習を高速化させるFPGA Ring-Allreduceの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2020-02-20"},"_buckets":{"deposit":"fcbf36ed-0bc5-46d2-8060-aa38915c49a9"},"_deposit":{"id":"204975","pid":{"type":"depid","value":"204975","revision_id":0},"owners":[6748],"status":"published","created_by":6748},"item_title":"分散深層学習を高速化させるFPGA Ring-Allreduceの検討","author_link":["508406","508409","508411","508407","508410","508408","508412","508413"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"分散深層学習を高速化させるFPGA Ring-Allreduceの検討"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンピュータシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2020-02-20","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"},{"subitem_text_value":"NTT"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/204975/files/IPSJ-Z82-7A-01.pdf","label":"IPSJ-Z82-7A-01.pdf"},"date":[{"dateType":"Available","dateValue":"2020-06-19"}],"format":"application/pdf","filename":"IPSJ-Z82-7A-01.pdf","filesize":[{"value":"567.0 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"9cf69a6c-204f-4f0f-becc-031aa0f21bec","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2020 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田仲, 顕至"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"有川, 勇輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"伊藤, 猛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"寺田, 和彦"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"森田, 和孝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三浦, 史光"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"寺本, 純司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"坂本, 健"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"分散深層学習を短時間に実行するために、各計算機ノードの集団通信をRing-Allreduceで実行する先行事例がある。ただし従来例では、データがGPUまたはCPUに移動するため遅延が発生してしまう。我々は、Ring-Allreduceを実行するFPGA NICを提案する。加えて、通信のオーバーヘッドを最小限に抑えるために、GPU計算時間と通信時間をオーバーラップさせるアルゴリズムの提案、さらに、既存と深層学習フレームワークと異種デバイス制御言語から構成される生産性の高いソフトウェアスタックを提案する。評価結果として、32のバッチサイズで精度を低下させることなく通信オーバーヘッドを84.27％削減できることを確認した。また、4ノード学習システムを使用すると、合計学習時間の7％短縮を実現した。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"32","bibliographic_titles":[{"bibliographic_title":"第82回全国大会講演論文集"}],"bibliographicPageStart":"31","bibliographicIssueDates":{"bibliographicIssueDate":"2020-02-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2020"}]},"relation_version_is_last":true,"weko_creator_id":"6748"},"id":204975,"updated":"2025-06-05T06:25:03.420507+00:00","links":{},"created":"2025-01-19T01:07:09.578431+00:00"}