{"updated":"2025-01-19T20:31:15.322322+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00203507","sets":["1164:4088:10109:10110"]},"path":["10110"],"owner":"44499","recid":"203507","title":["HBMをバッファとするパケットスケジューラのFPGA設計と実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2020-02-24"},"_buckets":{"deposit":"87d032f1-8b47-4a84-ae19-814bd0e2c6d2"},"_deposit":{"id":"203507","pid":{"type":"depid","value":"203507","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"HBMをバッファとするパケットスケジューラのFPGA設計と実装","author_link":["501910","501909"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"HBMをバッファとするパケットスケジューラのFPGA設計と実装"},{"subitem_title":"A design and implementation of an HBM-based packet scheduler on FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ネットワーク，設計 他","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2020-02-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院情報理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/203507/files/IPSJ-IOT20048016.pdf","label":"IPSJ-IOT20048016.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-IOT20048016.pdf","filesize":[{"value":"838.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"43"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"c19c1a09-19ee-4009-843f-f5bd941fcef6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2020 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小林, 克志"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Katsushi, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12326962","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8787","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"インターネットルータのパケットスケジューラが必要とするバッファ容量は DRAM 以外に実現できないが，既存の DRAM 帯域性能では今後の広帯域化に対応できないことは明らかである．シリコンダイスタックによって既存の DRAM で広帯域を実現する High Bandwidth Memory (HBM) を利用した製品が登場している．本報告では HBM を利用したパケットスケジューラの設計・実装を示す.我々の実装では HBM 理論最大帯域の 75% の転送性能を実現した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Although only DRAM can realize buffer sizes required by packet schedulers in Internet routers, it is obvious that existing its bandwidth capacities cannot satisfy the bandwidths\ngrowth in the future. High Bandwidth Memory (HBM) that significantly improves DRAM bandwidth throughputs by using silicon die stacking is emerging in the market. This report presents a design and implementation of an HBM-based packet scheduler on FPGA. Our HBM based scheduler implementation performed 75% of theoretical bandwidth of the HBM.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告インターネットと運用技術（IOT）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2020-02-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"16","bibliographicVolumeNumber":"2020-IOT-48"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:05:55.214815+00:00","id":203507,"links":{}}