{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00200100","sets":["1164:1579:9681:9960"]},"path":["9960"],"owner":"44499","recid":"200100","title":["高位合成用DSLコンパイラを用いたSLAMアプリケーションのハードウェアアクセラレーション"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-11-06"},"_buckets":{"deposit":"72958d0c-d5f2-4445-9836-5ded5741a7fc"},"_deposit":{"id":"200100","pid":{"type":"depid","value":"200100","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"高位合成用DSLコンパイラを用いたSLAMアプリケーションのハードウェアアクセラレーション","author_link":["486053","486054","486052","486050","486048","486049","486051","486055"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位合成用DSLコンパイラを用いたSLAMアプリケーションのハードウェアアクセラレーション"}]},"item_type_id":"4","publish_date":"2019-11-06","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"大分工業高等専門学校"},{"subitem_text_value":"株式会社フィックスターズ"},{"subitem_text_value":"株式会社フィックスターズ"},{"subitem_text_value":"Fixstars Solutions Inc."},{"subitem_text_value":"産業技術大学院大学"},{"subitem_text_value":"九州大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/200100/files/IPSJ-ARC19238008.pdf","label":"IPSJ-ARC19238008.pdf"},"date":[{"dateType":"Available","dateValue":"2021-11-06"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC19238008.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9073d28f-fac4-4bf4-b2d2-fcf3d8482e51","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"原, 凌司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"谷本, 輝夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 優良"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"大澤, 隆志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"丸岡, 晃"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 拓郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"追川, 修一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 弘士"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"自己位置を推定するための手法として SLAM (Simultaneous Localization and Mapping) が用いられる．SLAM は周囲の環境の地図の作成 ／ 更新や地図内の自分の位置を推定するために，取得画像から特徴点を検出する機能やそれらを追跡する機能を持つ．これらの機能は SLAM での処理の大部分を占める．画像処理など定型処理の実行効率を高める手段として FPGA (Field-Programmable Gate Array) によるハードウェアアクセラレーションが注目されている．しかしながら，回路規模の問題から SLAM アプリケーション全体を FPGA 実装することは難しい．そこで，本研究では SLAM の実装の 1 つである ATAM を対象に機能の一部を FPGA 実装した．ATAM 主要機能のうち 4 機能のハードウェア化において，資源制約下でフレームレートを最大化するため，Halide DSL からハードウェアを生成可能なコンパイラを用いて設計パラメータ探索を行った．Zynq 評価ボードである ZCU102 を用いた評価の結果，ソフトウェア実行に比べフレームレートを最大で 4.82 倍向上可能であることが分かった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-11-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"2019-ARC-238"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":200100,"updated":"2025-01-19T21:27:07.495486+00:00","links":{},"created":"2025-01-19T01:03:48.069803+00:00"}