{"updated":"2025-01-19T21:55:39.000883+00:00","links":{},"id":198694,"created":"2025-01-19T01:02:52.052249+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00198694","sets":["6164:6165:7651:9882"]},"path":["9882"],"owner":"44499","recid":"198694","title":["バンドギャップ基準電源回路を対象としたBIST手法の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-08-21"},"_buckets":{"deposit":"2099987e-b6d2-4d86-bfc7-f49932ba3fbd"},"_deposit":{"id":"198694","pid":{"type":"depid","value":"198694","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"バンドギャップ基準電源回路を対象としたBIST手法の評価","author_link":["479570","479571","479573","479572"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"バンドギャップ基準電源回路を対象としたBIST手法の評価"},{"subitem_title":"Evaluation of BIST Scheme for Band Gap Reference Circuit","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計・評価","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2019-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"高知工科大学"},{"subitem_text_value":"高知工科大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/198694/files/IPSJ-DAS2019005.pdf","label":"IPSJ-DAS2019005.pdf"},"date":[{"dateType":"Available","dateValue":"2021-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2019005.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d4833d0a-3e40-4834-a978-45ba2185c428","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"猪岡, 柚香"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"橘, 昌良"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuka, Inooka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Tachibana","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文ではBGR（Band-Gap Reference）回路に対するMOSFETのオープンやショートなどの致命的な故障を検出するBIST手法の概要と実測による評価について述べる．提案した0.18μmCMOSテクノロジで設計したオンチップBIST手法は，外部テスト信号を使用し，カタストロフィック故障の検出を行う．論理素子からなるテスト応答解析器でBGR回路内から3つのテストポイントを取り，期待される正常値と比較し，得られたテスト結果をデジタル信号として出力する．シミュレーションでは，8.8%の低い面積オーバヘッドで92.4%の高い故障検出率が得られた．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a Built-In Self-Test (BIST) scheme for detecting catastrophic faults of a MOSFET in the bandgap reference circuit and evaluation of this scheme. The proposed on-chip BIST scheme in 0.18-μm CMOS technology has offered catastrophic faults detection with external test signal. Output response analyzer composed of logical components compares expected voltages and observed voltages on three test-points in bandgap reference which is improved for test operation outputs the test result as a digital signal. The demonstrations show that fault coverage and area overhead are 92.4% and 8.8%, respectively.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"20","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2019論文集"}],"bibliographicPageStart":"15","bibliographicIssueDates":{"bibliographicIssueDate":"2019-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2019"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}