{"created":"2025-01-19T01:02:44.824430+00:00","updated":"2025-01-19T21:59:01.932468+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00198567","sets":["1164:6389:9696:9867"]},"path":["9867"],"owner":"44499","recid":"198567","title":["乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-07-16"},"_buckets":{"deposit":"290c5c5d-e914-4d2c-ab82-039bf3c58192"},"_deposit":{"id":"198567","pid":{"type":"depid","value":"198567","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計","author_link":["478979","478987","478989","478985","478980","478976","478977","478994","478981","478990","478992","478986","478991","478988","478982","478984","478983","478993","478978","478995"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計"},{"subitem_title":"Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2019-07-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東北大学/国立研究開発法人科学技術振興機構, さきがけ"},{"subitem_text_value":"インターステラテクノロジズ株式会社"},{"subitem_text_value":"神戸大学"},{"subitem_text_value":"神戸大学"},{"subitem_text_value":"神戸大学"},{"subitem_text_value":"NanyangTbchnologicalUniversity"},{"subitem_text_value":"Telecom ParisTech"},{"subitem_text_value":"Telecom ParisTech"},{"subitem_text_value":"Telecom ParisTech"},{"subitem_text_value":"東北大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Tohoku University / PRESTO, Japan Science and Technology Agency","subitem_text_language":"en"},{"subitem_text_value":"Interstellar Technologies, Inc.","subitem_text_language":"en"},{"subitem_text_value":"Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Nanyang Technological University","subitem_text_language":"en"},{"subitem_text_value":"Telecom ParisTech","subitem_text_language":"en"},{"subitem_text_value":"Telecom ParisTech","subitem_text_language":"en"},{"subitem_text_value":"Telecom ParisTech","subitem_text_language":"en"},{"subitem_text_value":"Tohoku University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing 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澄夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三浦, 典之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松田, 航平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"永田, 真"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shivam, Bhasin"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yves, Mathieu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tarik, Graba"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Jean-Luc, Danger"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"本間, 尚文"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Rei, Ueno","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Sumio, Morioka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Noriyuki, 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Homma","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12628305","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8671","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では高効率 AES ハードウェアアーキテクチャの設計を示す.提案アーキテクチャはレジスタリタイミングや命令順序交換に加え,本稿で新たに提案する線形演算の最適化手法である乗法的オフセットを用いることで高いスループット面積効率を達成する.さらに本稿では,論理合成の結果から,提案する AES 暗復号ハードウェアと AES 暗号化ハードウェアはそれぞれ既存手法よりも約 51-57 %と 58-64 %高いスループット面積効率を有することを示す.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents high throughput / gate hardware architectures. In order to achieve a high area-time efficinecy, the proposed architectures employ a new trick for optimizing construction of linear operations named multiplicative-offset, in addition to register-retiming and operation-reordering techniques. As a result of logic syntheses, we confirm that the proposed AES encryption /decryption hardware and encryption hardware acheive approximately 51-57% and 58-64% higher efficiency than conventional ones, respectively.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告セキュリティ心理学とトラスト(SPT)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-07-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"59","bibliographicVolumeNumber":"2019-SPT-34"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":198567,"links":{}}