{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00198531","sets":["1164:6389:9696:9867"]},"path":["9867"],"owner":"44499","recid":"198531","title":["パイプライン型剰余乗算器を用いたペアリング計算FPGAのサイドチャネルセキュリティ評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-07-16"},"_buckets":{"deposit":"47d6b0a0-4fe6-4a6f-a321-1e90064f1626"},"_deposit":{"id":"198531","pid":{"type":"depid","value":"198531","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"パイプライン型剰余乗算器を用いたペアリング計算FPGAのサイドチャネルセキュリティ評価","author_link":["478790","478789","478785","478784","478787","478788","478791","478786"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"パイプライン型剰余乗算器を用いたペアリング計算FPGAのサイドチャネルセキュリティ評価"},{"subitem_title":"Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2019-07-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"横浜国立大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Yokohama Nathional University","subitem_text_language":"en"},{"subitem_text_value":"Yokohama Nathional University","subitem_text_language":"en"},{"subitem_text_value":"Yokohama Nathional University","subitem_text_language":"en"},{"subitem_text_value":"Yokohama Nathional University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/198531/files/IPSJ-SPT19034023.pdf","label":"IPSJ-SPT19034023.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SPT19034023.pdf","filesize":[{"value":"2.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"46"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"7cbf568b-81ec-4382-b8fd-267e22a11d95","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics， Information and Communication Engineers This SIG report is only available to those in membership of the SIG．"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山﨑, 満文"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"坂本, 純一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"奥秋, 陽太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松本, 勉"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Mitsufumi, Yamazaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Junichi, Sakamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yota, Okuaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsutomu, Matsumoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12628305","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8671","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"双線形ペアリングは advanced cryptography を実現する際に有用であるため，その高速ハードウェア実装のサイドチヤネルセキュリティ評価が重要な課題となっている．我々は BN 曲線上の Optimal Ate ペアリングをパイプライン型剰余乗算器を用いて計算する最高速 FPGA 実装から抽出した主要部を SAKURA-X ボード上に実装した．我々はこの実装に対してサイドチャネル攻撃実験を行い，オリジナルのペアリング実装のサイドチャネルセキュリティにつき検討した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed hardware implementation is an important issue. We implemented on the SAKURA-X board the main part extracted from the fastest FPGA implementation that calculates the optimal Ate pairing on a BN curve using a pipelined modular multiplier. We performed side-channel attack experiments on this implementation and discussed side-channel security of the original pairing implementation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告セキュリティ心理学とトラスト（SPT）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-07-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"23","bibliographicVolumeNumber":"2019-SPT-34"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":198531,"updated":"2025-01-19T21:59:44.541536+00:00","links":{},"created":"2025-01-19T01:02:42.806389+00:00"}