{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00198499","sets":["1164:3925:9693:9866"]},"path":["9866"],"owner":"44499","recid":"198499","title":["高位設計フローにベイズ最適化法を応用した設計空間探索"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-07-16"},"_buckets":{"deposit":"d74ce826-47ab-45e1-ad8e-8007fec8bf99"},"_deposit":{"id":"198499","pid":{"type":"depid","value":"198499","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"高位設計フローにベイズ最適化法を応用した設計空間探索","author_link":["478595","478597","478596","478599","478598","478594"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位設計フローにベイズ最適化法を応用した設計空間探索"},{"subitem_title":"Design Space Search Applying Bayesian Optimization to High-level Design Flow","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2019-07-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科"},{"subitem_text_value":"東京大学大規模集積システム設計教育研究センター"},{"subitem_text_value":"東京大学大学院工学系研究科／東京大学大規模集積システム設計教育研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design Education Center","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo / VLSI Design Education Center","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/198499/files/IPSJ-CSEC19086058.pdf","label":"IPSJ-CSEC19086058.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-CSEC19086058.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"30"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"c7344243-738e-4951-a25e-558bbcb16a11","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics， Information and Communication Engineers This SIG report is only available to those in membership of the SIG．"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中山, 亮平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"粟野, 皓光"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"池田, 誠"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryohei, Nakayama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiromitsu, Awano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Makoto, Ikeda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11235941","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8655","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"回路規模がますます増大する昨今において，記述の抽象度が低いハードウェア設計言語ではなく，抽象度の高い高級プログラミング言語を用いて回路設計を行う高位合成技術が注目を集めている．一方で，高位合成に必要な動作周波数，ループ制約等の設計パラメータを決定するためには，効率的に設計空間を探索することが重要となる．本発表では，設計パラメータの探索にベイズ最適化法を用いて，局所解を避けながら最適解を求める手法を提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming languages with high abstraction levels, rather than hardware design languages with low abstraction levels, is drawing attention. On the other hand, it is important to search the design space efficiently in order to determine the design parameters such as the operating frequency and loop constraints required for high-level synthesis. In this presentation, we propose a method to find the optimal solution while avoiding local solutions by using Bayesian optimization for design parameter search.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告コンピュータセキュリティ（CSEC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-07-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"58","bibliographicVolumeNumber":"2019-CSEC-86"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T22:00:21.798238+00:00","created":"2025-01-19T01:02:41.015623+00:00","links":{},"id":198499}