{"created":"2025-01-19T01:01:58.055792+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00197513","sets":["1164:1579:9681:9819"]},"path":["9819"],"owner":"11","recid":"197513","title":["FPGAスイッチを用いたマルチGPU深層学習の高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-06-04"},"_buckets":{"deposit":"2176d4e7-8cb9-4f49-aea9-2bf15d80bff2"},"_deposit":{"id":"197513","pid":{"type":"depid","value":"197513","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FPGAスイッチを用いたマルチGPU深層学習の高速化","author_link":["473901","473903","473899","473902","473900","473898"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAスイッチを用いたマルチGPU深層学習の高速化"},{"subitem_title":"Accelerating Deep Learning for Multiple GPUs using FPGA Based Switch","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ニューラルネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2019-06-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/197513/files/IPSJ-ARC19236007.pdf","label":"IPSJ-ARC19236007.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC19236007.pdf","filesize":[{"value":"873.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"693e8105-6cf5-479d-b029-24e731adbeb4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"井坪, 知也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"竹本, 一馬"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 宏紀"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoya, Itsubo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuma, Takemoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroki, Matsutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"深層学習を用いた学習は大量の訓練データに対して大量の行列演算を行うため，学習の完了には膨大な時間がかかる．近年では，行列演算を高速に処理できる GPU (Graphics Processing Unit) を複数用いて並列に計算を行うことで高速に学習が行えることから，GPU 搭載マシンを相互接続したクラスタを使用した分散深層学習が広く利用されている．計算負荷という点では GPU による勾配計算が支配的ではあるが，このような分散深層学習においては GPU を搭載したホストマシンによる勾配集約のオーバヘッドも無視できない．そこで，本論文では，PCI-Express over 10Gbit Ethernet 技術を用いて GPU とホストマシンをリモート接続することで単一のホストマシンに接続されるGPU の数を増やす．そのうえで Ethernet でリモート接続された GPU とホスト間に勾配集約を専用回路で行う FPGA ベースの 10Gbit Ethernet スイッチを導入する．このように勾配計算をリモート GPU，勾配集約を FPGA スイッチで実現することで分散深層学習処理の高効率化を狙う．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-06-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2019-ARC-236"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"links":{},"id":197513,"updated":"2025-01-19T22:18:40.520066+00:00"}