{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00196142","sets":["6504:9795:9812"]},"path":["9812"],"owner":"6748","recid":"196142","title":["高位設計と低位設計の違いとFPGA演算性能の関係について"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-02-28"},"_buckets":{"deposit":"b958b52b-2dad-4feb-9990-fbefd4c3566a"},"_deposit":{"id":"196142","pid":{"type":"depid","value":"196142","revision_id":0},"owners":[6748],"status":"published","created_by":6748},"item_title":"高位設計と低位設計の違いとFPGA演算性能の関係について","author_link":["469097","469095","469098","469101","469096","469099","469100","469094"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位設計と低位設計の違いとFPGA演算性能の関係について"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンピュータシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2019-02-28","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"},{"subitem_text_value":"筑波大"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/196142/files/IPSJ-Z81-2L-07.pdf","label":"IPSJ-Z81-2L-07.pdf"},"date":[{"dateType":"Available","dateValue":"2019-05-27"}],"format":"application/pdf","filename":"IPSJ-Z81-2L-07.pdf","filesize":[{"value":"180.4 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"c946a32d-4181-4ee1-a355-2a7b5a1ef21d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"横野, 智也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山口, 佳樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤田, 典久"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小林, 諒平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"朴, 泰祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉川, 耕司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"安部, 牧人"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"梅村, 雅之"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA1チップの回路規模が100 万システムゲートを超えた現在，その全ての動作を把握し，RTL(Register Transfer Level)設計により完全な最適化を達成するのは困難になりつつある．そこで，高位記述言語によるHLS(High Level Synthesis) 設計に注目が集まっている．Intel社のIntel SDK for OpenCL，Xilinx 社のVivado HLS およびSDAccel などHLS 設計・開発環境は整いつつある．ここで，データセンターのような多くのユーザが利用しかつ複数のFPGA が並列に動作する環境において，RTL設計のみを唯一の選択肢とし続けることはユーザビリティの点から現実的ではない．一方，高性能演算と言う観点で設計手法をみたとき，HLS 設計のみを選択肢とするのは，現時点では時期尚早と考えられる．そこで本論文では，HDL 設計とHLS 設計の現状を等距離から評価し議論することで，次世代のヘテロジニアス高性能計算およびそこにFPGA が存在する可能性について検討する.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"60","bibliographic_titles":[{"bibliographic_title":"第81回全国大会講演論文集"}],"bibliographicPageStart":"59","bibliographicIssueDates":{"bibliographicIssueDate":"2019-02-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2019"}]},"relation_version_is_last":true,"weko_creator_id":"6748"},"id":196142,"updated":"2025-01-19T22:50:21.417695+00:00","links":{},"created":"2025-01-19T01:00:51.024165+00:00"}