{"links":{},"id":195540,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00195540","sets":["1164:2036:9683:9785"]},"path":["9785"],"owner":"11","recid":"195540","title":["ルネサスSOTB65nm用Through Chip Interface IPの実機評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-05-08"},"_buckets":{"deposit":"67909d86-2d3e-4df9-96ba-2529a62548b2"},"_deposit":{"id":"195540","pid":{"type":"depid","value":"195540","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ルネサスSOTB65nm用Through Chip Interface IPの実機評価","author_link":["465924","465926","465928","465930","465929","465927","465923","465925"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ルネサスSOTB65nm用Through Chip Interface IPの実機評価"},{"subitem_title":"The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2019-05-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/195540/files/IPSJ-SLDM19188006.pdf","label":"IPSJ-SLDM19188006.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM19188006.pdf","filesize":[{"value":"3.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"7f4586ee-7854-4ed2-8609-066e17f3e045","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"茅島, 秀人"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"四手井, 綱章"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideto, Kayashima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shidei, Tsunaaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Kojima","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ビルディングブロック型計算システムは，小規模なチップを誘導結合ワイヤレスチップ間接続 TCI（Thru-Chip Interface）により接続することで，様々なシステムを構築できる．2013年度～2017年度に実施された科学研究費基盤研究 S「ビルディングブロック型計算システムの研究」では，TCI の IP を様々なチップに組込むことで，様々にチップを組み合わせることで必要な性能と機能を持つシステムを実現することを目標とした．2013年度に開発した IP を組み込んだチップにより，2014年度に，CGRA（Coarse Grained Reconfigurable Accelerator） 3 枚の積層によるシステムの稼働を確認し，このデータを墓に2016年度，2017年度に MIPS 互換プロセッサ Geyser TT，Neural Network Accelerator SNACC，改良版 CGRA の CC-STOB2，Key Value Store 用 Accelerator KVS，ツインタワー積層用共有メモリチップ SMTT を開発した．これらのチップは全て単体では問題なく動作した．しかし，これらを積層してシステムを構築した所，設計通りには TCI が動作しない問題が発覚した．そこで，チップに組込まれた場合の IP の特性を測定するため TCITester を開発し，実チップにより，その特性を測定した．結果として，IP は安定して高い信頼性で動作はするが，性能は設計を下回った．これは IP 組み込みの際のパワーグリッドでの電圧低下，積層のために貧弱となった電源 I/O，ルネサス社 SOTB プロセス PDK の変更，ディジタル部とのインタフェースの問題の組み合わせが原因と推定される．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A building block computing system is made of various combinations of stacked small chips in 3D manner connected with wireless inductive TCI (Thru-Chip Interface). The JSPS Kiban-S project \"Study of Building Block Computing System\" (2013-2017) aimed to develop various prototypes with such chip-stacks. For this purpose, we developed a TCI IP using Renesas SOTB process in 2014. In 2015, 3-chip-stacks with CGRAs (Coarse Grained Reconfigurable Accelerators) with the TCI-IP was operational. Based on this evaluation results, we developed five chips providing the TCI IP: a MIPS compatible CPU Geyser TT, a neural network accelerator SNACC, key value store database accelerator KVS, improved version of CGRA CC-S0TB2, and the shared memory chip for twintower stacking SMTT in 2016 and 2017. Although all chips worked well as a single chip, when we build a system by stacking them, it appeared that the TCI IP did not work as designed. In order to investigate the reason, we developed a testing chip called TCI Tester, stack them and evaluated its electric characteristics. The evaluation result show that the IP is operational with a high reliability, but the performance is much lower than expected. The reason is supposed to be a combination of the voltage drop on the power grid, the poor power I/O for the limitation of the chip stacking, the change of PDK of Renesas SOTB process, and a problem of the digital interface.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-05-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2019-SLDM-188"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-19T01:00:27.785733+00:00","updated":"2025-01-19T23:03:26.570622+00:00"}