| Item type |
SIG Technical Reports(1) |
| 公開日 |
2019-05-08 |
| タイトル |
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タイトル |
SRAM-Based Synthesis for Multi-Output Gates |
| タイトル |
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言語 |
en |
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タイトル |
SRAM-Based Synthesis for Multi-Output Gates |
| 言語 |
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言語 |
eng |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
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資源タイプ |
technical report |
| 著者所属 |
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The University of Tokyo |
| 著者所属 |
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The University of Tokyo |
| 著者所属 |
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The University of Tokyo |
| 著者所属(英) |
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en |
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The University of Tokyo |
| 著者所属(英) |
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en |
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The University of Tokyo |
| 著者所属(英) |
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en |
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The University of Tokyo |
| 著者名 |
Xingming, Le
Amir, Masoud Gharehbaghi
Masahiro, Fujita
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| 著者名(英) |
Xingming, Le
Amir, Masoud Gharehbaghi
Masahiro, Fujita
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| 論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation with SRAM for multiple-output gates. Due to SRAM's multi-output nature and SRAM cell's compact structure, using multi-output gates to represent the circuit may become good for area efficiency if synthesized in an ideal way. We will compare the traditional implementation and SRAM-based implementation of look-up tables (LUTs) by modeling, and perform the synthesis by merging the nodes with several methods. Finally, we estimate the possibility of area reduction based on the experimental results. |
| 論文抄録(英) |
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内容記述タイプ |
Other |
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内容記述 |
Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation with SRAM for multiple-output gates. Due to SRAM's multi-output nature and SRAM cell's compact structure, using multi-output gates to represent the circuit may become good for area efficiency if synthesized in an ideal way. We will compare the traditional implementation and SRAM-based implementation of look-up tables (LUTs) by modeling, and perform the synthesis by merging the nodes with several methods. Finally, we estimate the possibility of area reduction based on the experimental results. |
| 書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA11451459 |
| 書誌情報 |
研究報告システムとLSIの設計技術（SLDM）
巻 2019-SLDM-188,
号 5,
p. 1-6,
発行日 2019-05-08
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| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
2188-8639 |
| Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
| 出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |
IPSJ-SLDM19188005.pdf (660.6 kB)
