{"links":{},"id":195135,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00195135","sets":["1164:1579:9681:9756"]},"path":["9756"],"owner":"44499","recid":"195135","title":["レジスタ変数削減によるサイクルベース型シミュレーションの高速化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-03-10"},"_buckets":{"deposit":"ddbf5d18-77a6-45f9-aadc-705775b4979d"},"_deposit":{"id":"195135","pid":{"type":"depid","value":"195135","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"レジスタ変数削減によるサイクルベース型シミュレーションの高速化手法","author_link":["463822","463823","463824","463821"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"レジスタ変数削減によるサイクルベース型シミュレーションの高速化手法"},{"subitem_title":"Speed-up Method of Cycle-based Simulation by reducing Register Variables","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"計算手法","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2019-03-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"(株)富士通研究所"},{"subitem_text_value":"(株)富士通研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu Laboratories, Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Laboratories, Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/195135/files/IPSJ-ARC19235055.pdf","label":"IPSJ-ARC19235055.pdf"},"date":[{"dateType":"Available","dateValue":"2021-03-10"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC19235055.pdf","filesize":[{"value":"967.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"926dc43c-688b-49de-84fe-82c21175e301","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田宮, 豊"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"池, 敦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yutaka, Tamiya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Atsushi, Ike","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年のプロセッサ等の大規模回路は非常に多くのレジスタを有しており，論理シミュレーション中に行われるレジスタ変数の更新回数の多さがシミュレーション速度の低下要因となっている．本論文では，レジスタ変数を削減するように回路記述を変換することにより，サイクルベース型シミュレーションの高速化手法を提案する．先ず，我々は “ブロッキング変数” を新たに提案し，シミュレーション結果を変えずにレジスタ変数をブロッキング変数に置換できる事を示す．本来は並列に評価されるプロセスを逐次的に評価することで，レジスタ変数からブロッキング変数への置換を促進する効果がある事を示す．更に，この効果を，回路モデル中の全プロセスと全レジスタ変数に対する依存関係として抽出して，最適なプロセス評価順序を求めるレジスタ変数の削減問題として定式化する．実験評価では，SystemC 標準シミュレータを用いた社内開発プロセッサ向け性能評価用論理シミュレータに本手法を適用した．その結果，SystemC 標準シミュレータを用いたシミュレーションは 3.16 倍高速化された．また，レジスタ変数削減により SystemC 標準シミュレータのマルチスレッド化が可能となり，最終的に SystemC の元記述に比べて 7.51 倍の高速化を達成した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, large-scale digital circuits, such as CPU processors, have enormous number of registers, which is one of the causes that result in their long logic simulation time. In this paper, we propose a method to speed up the cycle-based simulation by reducing register variables as pre-processing of logic simulation. First, we introduce a “blocking variable”, with which a register variable in the target circuit can be replaced without changing the result of the logic simulation. By sequentially evaluating processes in the target circuit model, which originally shall be evaluated in parallel, we can increase the possibility to reduce the register variables of the model. Furthermore, by extracting the dependencies between all processes and all register variables of the circuit model, we formulate the register variables reduction problem that finds the optimum process evaluation order. In our experiments, we've applied our proposed method to our in-house performance evaluation simulator, which uses SystemC standard simulation engine. As a result, we've sped up the simulator by 3.16 times in single thread mode, and by 7.51 times in multi-thread mode.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-03-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"55","bibliographicVolumeNumber":"2019-ARC-235"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:00:08.932117+00:00","updated":"2025-01-19T23:12:17.547798+00:00"}