{"links":{},"id":194179,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00194179","sets":["1164:1579:9681:9685"]},"path":["9685"],"owner":"44499","recid":"194179","title":["FPGA上での部分再構成を使用したストリーム向けクロスバの実装と検証"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-01-23"},"_buckets":{"deposit":"ec19139e-a58f-431f-b6ee-5b18886d5a79"},"_deposit":{"id":"194179","pid":{"type":"depid","value":"194179","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGA上での部分再構成を使用したストリーム向けクロスバの実装と検証","author_link":["457108","457103","457104","457101","457107","457102","457105","457106"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA上での部分再構成を使用したストリーム向けクロスバの実装と検証"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アプリケーション","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2019-01-23","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"長崎大学大学院工学研究科"},{"subitem_text_value":"理化学研究所計算科学研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer and Information Sciences, Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer and Information Sciences, Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer and Information Sciences, Graduate School of Engineering, Nagasaki University","subitem_text_language":"en"},{"subitem_text_value":"RIKEN Center for Computational Science","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/194179/files/IPSJ-ARC19234020.pdf","label":"IPSJ-ARC19234020.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC19234020.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"9e7abe46-da71-49ab-8c7a-29e5cfdab373","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川俣, 裕一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"木田, 智大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柴田, 裕一郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐野, 健太郎"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuichi, Kawamata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomohiro, Kida","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuichiro, Shibata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kentaro, Sano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では，複数の FPGA を用いるマルチ FPGA クラスタ計算システムにおいて，部分再構成を用いたネットワーククロスバの実装を提案する．部分再構成によりクロスバモジュールを再構成することで，ネットワークルーティングを変更できる．本稿の目的は通常回路と部分再構成回路の比較を行い，部分再構成を使用したクロスバの資源使用量，最大動作周波数を明らかにし，検証，評価を行い，今後の課題について明らかにすることである．結果として，部分再構成を使用することで，通常回路より ALM 資源の使用量を減らすことができた．一方，最大動作周波数はクロスバの入出力 bit 数が低い場合通常回路より高くなるが，入出力 bit 数が高くなるにつれ低下し，4096 bit の時では通常回路と同程度となった．現在は部分再構成に JTAG インタフェースを使用しているため，今後内部メモリからの高速な部分再構成について検討し，システムに最適なクロスバ設計を検討していく必要がある．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-01-23","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"20","bibliographicVolumeNumber":"2019-ARC-234"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T00:59:16.548925+00:00","updated":"2025-01-19T23:40:43.809874+00:00"}