{"links":{},"id":194165,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00194165","sets":["1164:1579:9681:9685"]},"path":["9685"],"owner":"44499","recid":"194165","title":["3Dフラッシュメモリの製造技術を用いた積層型全加算器の設計法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2019-01-23"},"_buckets":{"deposit":"66c52b8a-90c6-45f1-a99b-945597bf8c0a"},"_deposit":{"id":"194165","pid":{"type":"depid","value":"194165","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"3Dフラッシュメモリの製造技術を用いた積層型全加算器の設計法","author_link":["457004","457003","457002"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"3Dフラッシュメモリの製造技術を用いた積層型全加算器の設計法"},{"subitem_title":"Study of stacked full adder circuit with fabrication technology of 3D flash memory.","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路とシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2019-01-23","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"湘南工科大学情報工学科"},{"subitem_text_value":"湘南工科大学情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Information Science, Shonan Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Information Science, Shonan Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Information Science, Shonan Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/194165/files/IPSJ-ARC19234006.pdf","label":"IPSJ-ARC19234006.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC19234006.pdf","filesize":[{"value":"2.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"c950f735-7c0e-4a9d-a752-ec93a595ac27","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2019 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鈴木, 章矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡辺, 重佳"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Fumiya, Suzuki Shigeyoshi Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"3D フラッシュメモリの製造技術を用いた積層型全加算器の新しい回路設計法を提案した．展開方式，複合方式 1，複合方式 2，コンパクト方式，2 入力 NAND / NOR，3 入力 NAND / NAND 等の様々な積層型全加算器を設計し，トランジスタ数，シリコン柱数，パターン面積を従来の方式と比較した．その結果，展開方式では 48%，複合方式 1 では 28%，複合方式 2 では 25%，コンパクト方式では 21%，2 入力 NAND / NOR 方式では 17%，3 入力 NAND / NAND では 29% 従来の方式と比較してパターン面積を縮小できることがわかった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Novel new stacked type logic circuit with fabrication technology of 3D flash memory has been newly proposed. Designed stacked full adder circuit such as the expansion scheme, composite gate scheme 1, composite gate scheme 2, compact scheme, 2 inputs NAND / NOR scheme and 3 inputs NAND / NAND scheme, are compared the number of transistors, the number of silicon pillars and the pattern area with the conventional scheme. Number of pattem area of expansion scheme is by about 48% smaller than conventional scheme. In addition, composite gate scheme 1, composite gate scheme 2, compact scheme, 2 inputs NAND / NOR scheme and 3 inputs NAND / NAND scheme can be reduced by 28%, 25%, 21%, 17% and 29%, respectivery.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2019-01-23","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2019-ARC-234"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T00:59:15.767658+00:00","updated":"2025-01-19T23:40:59.909669+00:00"}