Abnormal Traffic Detection Circuit with Real-time Cardinality Counter

• Item type: Journal(1)
• 公開日: 2018-09-15
• タイトル: Abnormal Traffic Detection Circuit with Real-time Cardinality Counter
• タイトル / 言語: en
• タイトル: Abnormal Traffic Detection Circuit with Real-time Cardinality Counter
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [特集：“Applications and the Internet” in Conjunction with Main Topics of COMPSAC 2017] real-time traffic analysis, simple frequent-itemset-mining, self-timed pipeline
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Faculty of Engineering, Information and Systems, University of Tsukuba
• 著者所属: Faculty of Engineering, Information and Systems, University of Tsukuba
• 著者所属: Faculty of Business Sciences, University of Tsukuba
• 著者所属: Headquarters for International Industry-University Collaboration, University of Tsukuba
• 著者所属(英): en
• 著者所属(英): Faculty of Engineering, Information and Systems, University of Tsukuba
• 著者所属(英): en
• 著者所属(英): Faculty of Engineering, Information and Systems, University of Tsukuba
• 著者所属(英): en
• 著者所属(英): Faculty of Business Sciences, University of Tsukuba
• 著者所属(英): en
• 著者所属(英): Headquarters for International Industry-University Collaboration, University of Tsukuba
• 著者名: Shuji, Sannomiya; Akira, Sato; Kenichi, Yoshida; Hiroaki, Nishikawa
• 著者名(英): Shuji, Sannomiya; Akira, Sato; Kenichi, Yoshida; Hiroaki, Nishikawa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: To identify abnormal traffic such as P2P flows, DDoS attacks, and Internet worms, this paper discusses a circuit design to realize real-time abnormal traffic detection in broadband networks. Real-time counting of cardinality is the key feature of the circuit. Although our previous study showed that cardinality counting is effective for detecting various types of abnormal traffic, the slowness of DRAM access prevented us from deploying cardinality counting in backbone networks. To address the problem of DRAM access time, this paper proposes a new algorithm for cardinality counting. By changing the order of the cardinality counting process, the proposed algorithm enables parallel accesses of DRAM circuits, which hides the slow DRAM access time through a pipeline circuit. In addition, we propose a new hashing function that also hides the DRAM access problem. It partially replaces scattered addresses with successive addresses, in order to use a faster DRAM burst access. We also report the accuracy of the cardinality counting of the new algorithm, and describe the estimated processing performance based on a pipeline tact level circuit simulation. Our experimental results show that the use of the self-timed pipeline circuit can help realize cardinality counting at rates up to 100Gbps.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.26(2018) (online); DOI http://dx.doi.org/10.2197/ipsjjip.26.590; ------------------------------
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: To identify abnormal traffic such as P2P flows, DDoS attacks, and Internet worms, this paper discusses a circuit design to realize real-time abnormal traffic detection in broadband networks. Real-time counting of cardinality is the key feature of the circuit. Although our previous study showed that cardinality counting is effective for detecting various types of abnormal traffic, the slowness of DRAM access prevented us from deploying cardinality counting in backbone networks. To address the problem of DRAM access time, this paper proposes a new algorithm for cardinality counting. By changing the order of the cardinality counting process, the proposed algorithm enables parallel accesses of DRAM circuits, which hides the slow DRAM access time through a pipeline circuit. In addition, we propose a new hashing function that also hides the DRAM access problem. It partially replaces scattered addresses with successive addresses, in order to use a faster DRAM burst access. We also report the accuracy of the cardinality counting of the new algorithm, and describe the estimated processing performance based on a pipeline tact level circuit simulation. Our experimental results show that the use of the self-timed pipeline circuit can help realize cardinality counting at rates up to 100Gbps.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.26(2018) (online); DOI http://dx.doi.org/10.2197/ipsjjip.26.590; ------------------------------
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 59, 号 9, 発行日 2018-09-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764