{"id":190899,"updated":"2025-01-20T01:00:26.536636+00:00","links":{},"created":"2025-01-19T00:56:50.346955+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00190899","sets":["6164:6165:7651:9542"]},"path":["9542"],"owner":"11","recid":"190899","title":["積和演算ライブラリを用いたCyberWorkBench<sup>(R)</sup>高位合成フロー"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-08-22"},"_buckets":{"deposit":"401e0135-a109-419c-b838-63a396e5a48f"},"_deposit":{"id":"190899","pid":{"type":"depid","value":"190899","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"積和演算ライブラリを用いたCyberWorkBench<sup>(R)</sup>高位合成フロー","author_link":["438153","438161","438156","438154","438160","438162","438157","438151","438152","438158","438155","438159"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"積和演算ライブラリを用いたCyberWorkBench<sup>(R)</sup>高位合成フロー"},{"subitem_title":"Multiply-Accumulate Class Library for CyberWorkBench<sup>(R)</sup> Highlevel Synthesis","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2018-08-22","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本電気株式会社"},{"subitem_text_value":"日本電気株式会社"},{"subitem_text_value":"日本電気株式会社"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"兵庫県立大学"},{"subitem_text_value":"日本電気株式会社"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"NEC Corporation.","subitem_text_language":"en"},{"subitem_text_value":"NEC Corporation.","subitem_text_language":"en"},{"subitem_text_value":"NEC Corporation.","subitem_text_language":"en"},{"subitem_text_value":"Nagoya University","subitem_text_language":"en"},{"subitem_text_value":"University of Hyogo","subitem_text_language":"en"},{"subitem_text_value":"NEC Corporation.","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/190899/files/IPSJ-DAS2018014.pdf","label":"IPSJ-DAS2018014.pdf"},"date":[{"dateType":"Available","dateValue":"2020-08-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2018014.pdf","filesize":[{"value":"1.6 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一敏"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tamotsu, Sakai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tetsuya, Aoyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Wataru, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinya, Honda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yukikazu, Nakamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazutoshi, Wakabayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，積和演算ライブラリを高位合成ツール上で実現するフローを提案する．まず，既存の高位合成ツール上の FIR フィルタ専用ライブラリで実現されているハードウェア構造を一般化し，本ハードウェア構造は従来適用対象であったパイプライン回路だけでなく順序回路においても使用可能であること，また DSP ブロックの適切な利用により高性能なデザイン生成が可能であることを示した．高位合成ツール上で本ハードウェア構造を実現する為，積和演算ライブラリ関数の呼出し部を適切な単位で分割し，各分割単位を多サイクル入力型のパイプライン演算器として合成するフローを提案した．本フローを高位合成ツール CyberWorkBench (R) 上に構築し，より高性能なデザインが得られていることを確認した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes a high level synthesis design flow using the class library for multiply-accumulate (MAC) operation. Firstly, we generalize the hardware structure which is synthesized from the library dedicated for FIR filter on conventional high-level synthesis tool.We then indicate this generalized structure can be used in sequential circuit design as well as pipelined circuit design and a high performance design can be gained by taking full advantage of functionality provided in the embedded DSP blocks. To synthesize this generalized structure from high level synthesis tool, we propose high level synthesis design flow: MAC library function call is divided into several units and each division unit is synthesized as a pipelined operator with input at multiple cycles. Applying this proposed flow to high level synthesis tool CyberWorkBench (R), high-performance designs in a various range of applications can be gained.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"74","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2018論文集"}],"bibliographicPageStart":"69","bibliographicIssueDates":{"bibliographicIssueDate":"2018-08-22","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2018"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}