{"id":190898,"updated":"2025-01-20T01:00:25.421216+00:00","links":{},"created":"2025-01-19T00:56:50.292012+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00190898","sets":["6164:6165:7651:9542"]},"path":["9542"],"owner":"11","recid":"190898","title":["高位合成時のモジュール分割におけるバッファコスト最小化問題とその解法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-08-22"},"_buckets":{"deposit":"650bb588-c558-4d18-ac0f-366a308928c6"},"_deposit":{"id":"190898","pid":{"type":"depid","value":"190898","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"高位合成時のモジュール分割におけるバッファコスト最小化問題とその解法","author_link":["438149","438148","438147","438150","438146"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位合成時のモジュール分割におけるバッファコスト最小化問題とその解法"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2018-08-22","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"富士通研究所"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工・情報通信専攻"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Laboratories Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Communications Engineering, Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/190898/files/IPSJ-DAS2018013.pdf","label":"IPSJ-DAS2018013.pdf"},"date":[{"dateType":"Available","dateValue":"2020-08-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2018013.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"a3db28ec-a605-486e-b91f-1e65e4ace61d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大場, 諒介"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田宮, 豊"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"従来 CPU 上で実行していた大規模演算を高速に処理する目的から，ハードウェアアクセラレータ設計に対する需要が高まっている．現在は Xilinx 社 Vivado-HLS 等の商用高位合成ツールが実用段階にあり，ソフトウェアからハードウェアを効率的に合成できる．一方，ツールが一度に高位合成可能なソフトウェアの規模には限界があることから，通常は複数のモジュールに分けてハードウェアを設計する．このような設計方法においては，個々に設計されたハードウェアモジュールを統合する際にタイミング調整用の遅延バッファが必要となるため，挿入されるバッファのコストを考慮してモジュール分割することが求められる．本稿では，高位合成時のモジュール分割によって挿入されるバッファコストを定量化し，バッファコスト最小化問題を定式化する．さらに，バッファコスト最小化問題に対する優良解を効率的に探索する部分結合法を提案する．計算機シミュレーションの結果，貪欲法を用いた探索に比べ，部分結合法は平均 23.5% バッファコストを削減することに成功した．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"68","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2018論文集"}],"bibliographicPageStart":"63","bibliographicIssueDates":{"bibliographicIssueDate":"2018-08-22","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2018"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}