{"updated":"2025-01-20T01:00:19.960134+00:00","links":{},"id":190893,"created":"2025-01-19T00:56:50.010695+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00190893","sets":["6164:6165:7651:9542"]},"path":["9542"],"owner":"11","recid":"190893","title":["バンドギャップ基準電源回路を対象としたBIST手法の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-08-22"},"_buckets":{"deposit":"49bf7416-9f60-4306-876f-97b0987bbac5"},"_deposit":{"id":"190893","pid":{"type":"depid","value":"190893","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"バンドギャップ基準電源回路を対象としたBIST手法の検討","author_link":["438101","438100","438102","438099"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"バンドギャップ基準電源回路を対象としたBIST手法の検討"},{"subitem_title":"A BIST Scheme for Band Gap Reference Circuit","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2018-08-22","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"高知工科大学"},{"subitem_text_value":"高知工科大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/190893/files/IPSJ-DAS2018008.pdf","label":"IPSJ-DAS2018008.pdf"},"date":[{"dateType":"Available","dateValue":"2020-08-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2018008.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"330","billingrole":"44"}],"accessrole":"open_date","version_id":"2bad54bd-6e6c-4165-8164-d48030582bab","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"猪岡, 柚香"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"橘, 昌良"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuka, Inooka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Tachibana","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では，ミックストシグナル LSI でよく用いられる参照電源電圧一つである BGR （Band-Gap Reference） 回路に対する MOSFET のオープンやショートなどの致命的な故障を検出する BIST 手法について述べる．提案 BIST では BGR 回路内から 3 つのテストポイントを取り，期待される正常値と比較することで故障を検出している．また，スタートアップ回路内にテスト入力発生器を組み込むことで高密度集積を可能としている．シミュレーションでは，8.8% の低い面積オーバヘッドで 91.4% の高い故障検出率が得られた．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a Built-In Self-Test (BIST) scheme for detecting catastrophic faults such as opening and shorting of a MOSFET in the Bandgap reference which is one of reference voltages often used in mixed-signal LSI. The proposed BIST technique detects catastrophic faults by comparing expected voltages and observed voltages on three test-points in bandgap reference which is improved for test operation. Furthermore, since test stimulus generator is incorporated into a startup circuit, the high-density integration becomes possible. The demonstrations show that fault coverage and area overhead are 91.4% and 8.8%, respectively.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"38","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2018論文集"}],"bibliographicPageStart":"33","bibliographicIssueDates":{"bibliographicIssueDate":"2018-08-22","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2018"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}