{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00190687","sets":["1164:1579:9341:9527"]},"path":["9527"],"owner":"11","recid":"190687","title":["10G Ethernet向けデータパス拡張を適用したRISC-Vプロセッサの提案と実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-07-23"},"_buckets":{"deposit":"cfa85403-c3c0-4c50-94fc-5f4b62b21de1"},"_deposit":{"id":"190687","pid":{"type":"depid","value":"190687","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"10G Ethernet向けデータパス拡張を適用したRISC-Vプロセッサの提案と実装","author_link":["437092","437096","437093","437087","437089","437088","437094","437091","437095","437090"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"10G Ethernet向けデータパス拡張を適用したRISC-Vプロセッサの提案と実装"},{"subitem_title":"Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサアーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-07-23","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学環境情報学部"},{"subitem_text_value":"慶應義塾大学環境情報学部"},{"subitem_text_value":"慶應義塾大学理工学研究科"},{"subitem_text_value":"慶應義塾大学環境情報学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Environment and Information Studies, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Environment and Information Studies, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Environment and Information Studies, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/190687/files/IPSJ-ARC18232005.pdf","label":"IPSJ-ARC18232005.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC18232005.pdf","filesize":[{"value":"507.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"7e01a217-d927-4ea4-9478-42478116d037","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"矢内, 洋祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 健史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"空閑, 洋平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"徳差, 雄太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"村井, 純"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yosuke, Yanai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takeshi, Matsuya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yohei, Kuga","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuta, Tokusashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Jun, Murai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では，パケット処理を目的とした 1024 bit 幅のデータパスを持ったプロセッサを提案する．Intel DPDK を代表とするソフトウェアパケット処理環境は，高クロックかつマルチコア CPU を利用し，10G ・ 100G Ethernet 環境での高速パケット処理を実現している．本提案機能拡張では，Ethernet PHY とのデータをやり取りする 1024 bit 幅のデータパスを CPU に接続することで，シングルコアかつ低クロックでの高速パケット処理の実現を目的とする．本論文では，FPGA を用いて 32 bit RISC-V プロセッサと，本提案手法の拡張を実装した．評価では，ルーティングの一部処理を行いながら 10G Ethernet のラインレートに対して 99.1% のスループットでのパケット処理が可能なことを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing environment typified by Intel DPDK realizes high-speed packet processing in a 10 G / 100 G Ethernet environment using a high clock and multi-core CPU. In this proposed function extension, we aim to realize high-speed packet processing with single core and low clock by connecting 1024 bit wide data path that exchanges data with Ethernet PHY to CPU. In this paper, we implemented 32bit RISC-V processor and extension of our proposed method using FPGA. In the evaluation, we confirmed that it is possible to process packets with throughput of 99.1% with respect to the line rate of 10 G Ethernet while processing part of routing.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-07-23","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2018-ARC-232"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":190687,"updated":"2025-01-20T01:05:25.454555+00:00","links":{},"created":"2025-01-19T00:56:38.463366+00:00"}