{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00189773","sets":["1164:1579:9341:9500"]},"path":["9500"],"owner":"11","recid":"189773","title":["競合アクセスを投機的に許可するトランザクショナルメモリの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-06-07"},"_buckets":{"deposit":"8c815650-7aca-47e5-b0c6-a5c254270f4f"},"_deposit":{"id":"189773","pid":{"type":"depid","value":"189773","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"競合アクセスを投機的に許可するトランザクショナルメモリの検討","author_link":["432784","432786","432781","432785","432782","432783"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"競合アクセスを投機的に許可するトランザクショナルメモリの検討"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリサブシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-06-07","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"名古屋工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya 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知紀"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"林, 昌樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"二間瀬, 悠希"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"塩谷, 亮太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"五島, 正裕"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチコア環境では一般に，ロックを用いて共有変数へのアクセスを調停する．しかし，ロックにはデッドロックの発生や並列度の低下などの問題があるため，ロックを使用しない並行性制御機構として，トランザクショナルメモリ （TM） が提案されている．この機構をハードウェア上に実装したハードウェア ・ トランザクショナルメモリ （HTM） では，トランザクション （Tx） を投機的に並列実行することで，ロックに比べ並列度が向上する．しかし，HTM では同一共有変数へのアクセスが頻発すると性能が低下してしまうため，アクセス競合を極力回避する必要がある．一般に Tx には，ある共有変数に対する read ・ write アクセスが完了した後にも，コミットまで長時間処理が継続するものがある．このような場合，当該 Tx においてその変数に再度アクセスしないにも関わらず，当該変数に対する他スレッドによるアクセスは競合として検出され，並列性が損なわれてしまう．本稿では，Tx 内でアクセス済みの共有変数に対し，Tx をコミットする前であっても他のスレッドによる read および write アクセスを投機的に許可するスケジューリング手法を提案し，それに伴うコヒーレンシ制御について議論する． 提案手法を LogTM に実装し評価を行った結果，平均 63.6%，最大 38.8% の性能向上を達成した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"9","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-06-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2018-ARC-231"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":189773,"updated":"2025-01-20T01:29:03.496255+00:00","links":{},"created":"2025-01-19T00:55:46.994940+00:00"}