{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00187537","sets":["6504:9465:9473"]},"path":["9473"],"owner":"6748","recid":"187537","title":["ThruChip Interfaceを用いたコア間ネットワーク"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-03-13"},"_buckets":{"deposit":"8236acc0-3eee-4aea-a4fd-72de63feb348"},"_deposit":{"id":"187537","pid":{"type":"depid","value":"187537","revision_id":0},"owners":[6748],"status":"published","created_by":6748},"item_title":"ThruChip Interfaceを用いたコア間ネットワーク","author_link":["424682","424680","424679","424681"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ThruChip Interfaceを用いたコア間ネットワーク"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンピュータシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2018-03-13","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶大"},{"subitem_text_value":"慶大"},{"subitem_text_value":"慶大"},{"subitem_text_value":"慶大"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/187537/files/IPSJ-Z80-3A-02.pdf","label":"IPSJ-Z80-3A-02.pdf"},"date":[{"dateType":"Available","dateValue":"2018-04-25"}],"format":"application/pdf","filename":"IPSJ-Z80-3A-02.pdf","filesize":[{"value":"302.2 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"e0a3b00d-e8a3-4afa-ac91-7da108cac29b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"門本, 淳一郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"宮田, 知輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"黒田, 忠広"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"誘導結合を用いたワイヤレスチップ間接続技術であるThruChip Interface (TCI) は,積層した複数のチップ間に高速なネットワークを構築できる.TCI の利用を容易にするため,65nm SOI CMOSプロセス向けのIPコアを開発した.IPコアは,オンチップインダクタと送受信機,SerDesから成るハードIPと,ピギーバック方式のACK信号転送に基づくフロー制御機構を内蔵するリンクおよびルータのソフトIPから構成される.本稿では,ハードIPの回路構成とその動作,ソフトIPの実現するネットワーク構成とフロー制御について述べる.また,IPのデータ転送速度,消費電力について,実チップを用いた評価結果を示す.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"12","bibliographic_titles":[{"bibliographic_title":"第80回全国大会講演論文集"}],"bibliographicPageStart":"11","bibliographicIssueDates":{"bibliographicIssueDate":"2018-03-13","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2018"}]},"relation_version_is_last":true,"weko_creator_id":"6748"},"id":187537,"updated":"2025-01-20T02:12:12.995928+00:00","links":{},"created":"2025-01-19T00:54:12.280576+00:00"}