Evaluation of Three Quads Using Matrix Transpose

• Item type: Journal(1)
• 公開日: 2018-03-15
• タイトル: Evaluation of Three Quads Using Matrix Transpose
• タイトル / 言語: en
• タイトル: Evaluation of Three Quads Using Matrix Transpose
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [一般論文（テクニカルノート）] parallel processing, cluster computing, interconnection network, interactive simulation
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: University of Fukui
• 著者所属: University of Fukui
• 著者所属: Kyoto University／Presently with The Kyoto College of Graduate Studies for Informatics
• 著者所属(英): en
• 著者所属(英): University of Fukui
• 著者所属(英): en
• 著者所属(英): University of Fukui
• 著者所属(英): en
• 著者所属(英): Kyoto University / Presently with The Kyoto College of Graduate Studies for Informatics
• 著者名: Jiachao, Zhang; Shin-ichiro, Mori; Shinji, Tomita
• 著者名(英): Jiachao, Zhang; Shin-ichiro, Mori; Shinji, Tomita
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: For medium scale commodity cluster, a high cost performance interconnection network named Three Quads was proposed. Topological features of Three Quads include 1) diameter of two, 2) embed-ability of 3D torus and many well-known topologies, and 3) fault tolerance and path diversity. All the hardware components of Three Quads are essentially small-scale and off-the-shelf commodity hardware to achieve superior cost performance. In this paper, the performance of the Three Quads is evaluated using a matrix transpose application and results show that the Three Quads gives appealing performance comparable to a large scale and expensive enterprise switch fabric.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.26(2018) (online); DOI http://dx.doi.org/10.2197/ipsjjip.26.301; ------------------------------
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: For medium scale commodity cluster, a high cost performance interconnection network named Three Quads was proposed. Topological features of Three Quads include 1) diameter of two, 2) embed-ability of 3D torus and many well-known topologies, and 3) fault tolerance and path diversity. All the hardware components of Three Quads are essentially small-scale and off-the-shelf commodity hardware to achieve superior cost performance. In this paper, the performance of the Three Quads is evaluated using a matrix transpose application and results show that the Three Quads gives appealing performance comparable to a large scale and expensive enterprise switch fabric.; ------------------------------; This is a preprint of an article intended for publication Journal of; Information Processing(JIP). This preprint should not be cited. This; article should be cited as: Journal of Information Processing Vol.26(2018) (online); DOI http://dx.doi.org/10.2197/ipsjjip.26.301; ------------------------------
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 59, 号 3, 発行日 2018-03-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764