Implementation of ROS-Compliant FPGA Component of Image Processing Hardware using High Level Synthesis

• Item type: Symposium(1)
• 公開日: 2018-03-02
• タイトル: Implementation of ROS-Compliant FPGA Component of Image Processing Hardware using High Level Synthesis
• タイトル / 言語: en
• タイトル: Implementation of ROS-Compliant FPGA Component of Image Processing Hardware using High Level Synthesis
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: FPGA, ROS, Robot, High Level Synthesis, Image Processing
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_5794
• 資源タイプ: conference paper
• 著者所属: Graduate School of Engineering, Utsunomiya University
• 著者所属: Graduate School of Engineering, Utsunomiya University
• 著者所属: Graduate School of Engineering, Utsunomiya University
• 著者所属: Graduate School of Engineering, Utsunomiya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Utsunomiya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Utsunomiya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Utsunomiya University
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Utsunomiya University
• 著者名: Yuhei, Sugata; Takeshi, Ohkawa; Kanemitsu, Ootsu; Takashi, Yokota
• 著者名(英): Yuhei, Sugata; Takeshi, Ohkawa; Kanemitsu, Ootsu; Takashi, Yokota
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: The advancement of intelligents robot require high-performance image processing with low power consumption. FPGA (Field Programmable Gate Array) is expected to perform this image processing with low power consumption, however, the cost of developing FPGA is too high to introduce. To reduce the development cost, High Level Synthesis (HLS), which generates hardwired circuits from behavioral description written by C language, is effective. On the other hand, the use of ROS (Robot Operating System) is increasing for the development of intelligent robot system in order to reduce the development. We proposed "ROS-Compliant FPGA Component" to introduce FPGA into robot easily, by componentizing FPGA circuit into ROS node. In this presentation, the implementation of the ROS-Compliant FPGA component of image processing hardware using HLS is described. As an example, a detailed implementation of ROS-Compliant FPGA component with FAST feature point detection circuit, which is generated by using Xilinx Vivado-HLS and HLS video library based on OpenCV, is explained.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: The advancement of intelligents robot require high-performance image processing with low power consumption. FPGA (Field Programmable Gate Array) is expected to perform this image processing with low power consumption, however, the cost of developing FPGA is too high to introduce. To reduce the development cost, High Level Synthesis (HLS), which generates hardwired circuits from behavioral description written by C language, is effective. On the other hand, the use of ROS (Robot Operating System) is increasing for the development of intelligent robot system in order to reduce the development. We proposed "ROS-Compliant FPGA Component" to introduce FPGA into robot easily, by componentizing FPGA circuit into ROS node. In this presentation, the implementation of the ROS-Compliant FPGA component of image processing hardware using HLS is described. As an example, a detailed implementation of ROS-Compliant FPGA component with FAST feature point detection circuit, which is generated by using Xilinx Vivado-HLS and HLS video library based on OpenCV, is explained.
• 書誌情報: 組込みシステムワークショップ2017論文集; 巻 2017, p. 23-23, 発行日 2018-03-02
• 出版者 / 言語: ja
• 出版者: 情報処理学会