Variability and Statistical Design

• Item type: Trans(1)
• 公開日: 2008-08-27
• タイトル: Variability and Statistical Design
• タイトル / 言語: en
• タイトル: Variability and Statistical Design
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Invited Papers
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: University of Minnesota Minneapolis MN USA
• 著者所属(英): en
• 著者所属(英): University of Minnesota, Minneapolis, MN, USA
• 著者名: SachinS.Sapatnekar
• 著者名(英): Sachin, S.Sapatnekar
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With each technology generation the effects of on-chip variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g. drifts in channel length oxide thickness threshold voltage or doping concentration) which affect the circuit yield as well as variations in the environmental operating conditions (e.g. supply voltage or temperature) after the circuit is manufactured which impact the performance of the design. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power and variation-tolerant design is imperative for next-generation designs. This paper overviews research in this area describing methods for the analysis and optimization of statistical effects.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With each technology generation, the effects of on-chip variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage or temperature) after the circuit is manufactured, which impact the performance of the design. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power, and variation-tolerant design is imperative for next-generation designs. This paper overviews research in this area, describing methods for the analysis and optimization of statistical effects.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 1, p. 18-32, 発行日 2008-08-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会