Trends in Emerging On-Chip Interconnect Technologies

• Item type: Trans(1)
• 公開日: 2008-08-27
• タイトル: Trends in Emerging On-Chip Interconnect Technologies
• タイトル / 言語: en
• タイトル: Trends in Emerging On-Chip Interconnect Technologies
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Invited Papers
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: University of California Irvine / Presently with Colorado State University
• 著者所属: University of California Irvine
• 著者所属(英): en
• 著者所属(英): University of California, Irvine / Presently with Colorado State University
• 著者所属(英): en
• 著者所属(英): University of California, Irvine
• 著者名: Sudeep, Pasricha; Nikil, Dutt
• 著者名(英): Sudeep, Pasricha; Nikil, Dutt
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In deep submicron (DSM) VLSI technologies it is becoming increasingly harder for a copper based electrical interconnect fabric to satisfy the multiple design requirements of delay power bandwidth and delay uncertainty. This is because electrical interconnects are becoming increasingly susceptible to parasitic resistance and capacitance with shrinking process technology and rising clock frequencies which poses serious challenges for interconnect delay power dissipation and reliability. On-chip communication architectures such as buses and networks-on-chip (NoC) that are used to enable inter-component communication in multi-processor systems-on-chip (MPSoC) designs rely on these electrical interconnects at the physical level and are consequently faced with the entire gamut of challenges and drawbacks that plague copper-based electrical interconnects. To overcome the limitations of traditional copper-based electrical interconnects several research efforts have begun looking at novel interconnect alternatives such as on-chip optical interconnects wireless interconnects and carbon nanotube-based interconnects. This paper presents an overview and current state of research for these three promising interconnect technologies. We also discuss the existing challenges for each of these technologies that remain to be resolved before they can be adopted as replacements for copper-based electrical interconnects in the future.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In deep submicron (DSM) VLSI technologies, it is becoming increasingly harder for a copper based electrical interconnect fabric to satisfy the multiple design requirements of delay, power, bandwidth, and delay uncertainty. This is because electrical interconnects are becoming increasingly susceptible to parasitic resistance and capacitance with shrinking process technology and rising clock frequencies, which poses serious challenges for interconnect delay, power dissipation and reliability. On-chip communication architectures such as buses and networks-on-chip (NoC) that are used to enable inter-component communication in multi-processor systems-on-chip (MPSoC) designs rely on these electrical interconnects at the physical level, and are consequently faced with the entire gamut of challenges and drawbacks that plague copper-based electrical interconnects. To overcome the limitations of traditional copper-based electrical interconnects, several research efforts have begun looking at novel interconnect alternatives, such as on-chip optical interconnects, wireless interconnects and carbon nanotube-based interconnects. This paper presents an overview and current state of research for these three promising interconnect technologies. We also discuss the existing challenges for each of these technologies that remain to be resolved before they can be adopted as replacements for copper-based electrical interconnects in the future.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 1, p. 2-17, 発行日 2008-08-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会