{"id":186057,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00186057","sets":["1164:2240:9411:9412"]},"path":["9412"],"owner":"11","recid":"186057","title":["有限要素法における係数行列生成部のマルチコア・メニィコア向け最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-02-21"},"_buckets":{"deposit":"ebd90c0a-c2a7-466f-ad1c-961e0471bc5d"},"_deposit":{"id":"186057","pid":{"type":"depid","value":"186057","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"有限要素法における係数行列生成部のマルチコア・メニィコア向け最適化","author_link":["415869","415868","415871","415863","415862","415864","415866","415867","415865","415870"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"有限要素法における係数行列生成部のマルチコア・メニィコア向け最適化"},{"subitem_title":"Optimization of generation process for sparse coefficient matrices in FEM on multicore/manycore architectures","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"並列最適化","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-02-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学情報基盤センター／科学技術振興機構CREST"},{"subitem_text_value":"東京大学情報基盤センター／科学技術振興機構CREST"},{"subitem_text_value":"エヌビディア"},{"subitem_text_value":"東京大学情報基盤センター"},{"subitem_text_value":"東京大学情報基盤センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Information Technology Center, The University of Tokyo / CREST, Japan Science and Technology Agency","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Center, The University of Tokyo / CREST, Japan Science and Technology Agency","subitem_text_language":"en"},{"subitem_text_value":"NVIDIA Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Center, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Center, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/186057/files/IPSJ-HPC18163028.pdf","label":"IPSJ-HPC18163028.pdf"},"date":[{"dateType":"Available","dateValue":"2020-02-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC18163028.pdf","filesize":[{"value":"525.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"373d495a-c0d6-4079-b7b6-d879eb381126","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中島, 研吾"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"星野, 哲也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"成瀬, 彰"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"塙, 敏博"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三木, 洋平"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kengo, Nakajima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tetsuya, Hoshino","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Akira, Naruse","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshihiro, Hanawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yohei, Miki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8841","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"有限要素法は偏微分方程式のは値解法として広く計算科学 ・ 工学分野で使用されている．有限要素法では各要素における積分方程式から密な要素行列を生成し，それを重ね合わせて得られる疎な全体行列に境界条件を適用し，全体行列を係は行列とする連立一次方程式を解いて解を得る．要素行列 ・ 全体行列を生成する係は行列生成部は連立一次方程式求解と並んで時間を要するプロセスである．本研究では，Intel Xeon （Broadwell），Intel Xeon Phi （Knights Landing） および NVIDIA Tesla P100 （Pascal） 及び V100 （Volta） を対象としてそれぞれの特性を生かした最適化を実施した．本稿では最適化の詳細と性能評価結果について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Finite Element Method (FEM) is widely used for solving Partial Differential Equations (PDE) in various types of applications of computational science and engineering. In FEM, dense element matrix is introduced based on integral equations for each element, and sparse global matrix is assembled from element matrices. Boundary conditions are applied to this global matrix, and derived linear equations are solved. This process for generation of element and global matrices and the sparse matrix solver are the most expensive procedures in FEM procedures. In the present work, the matrix assembly process is optimized on Intel Xeon Phi (Broadwell), Intel Xeon Phi (Knights Landing) and NVIDIA Tesla P100 (Pascal) and V100 (Volta) based on features of each architecture. The paper describes details of optimization and results of performance evaluation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-02-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"28","bibliographicVolumeNumber":"2018-HPC-163"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"updated":"2025-01-20T02:44:33.958542+00:00","created":"2025-01-19T00:53:06.832595+00:00","links":{}}