{"updated":"2025-01-22T22:40:30.354725+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00018581","sets":["934:1119:1147:1150"]},"path":["1150"],"owner":"1","recid":"18581","title":["FPGAにおける差動信号入出力を用いたPCクラスタ用ネットワークインタフェース"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-05-15"},"_buckets":{"deposit":"19e8bb91-d768-4905-ab64-98334842b388"},"_deposit":{"id":"18581","pid":{"type":"depid","value":"18581","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAにおける差動信号入出力を用いたPCクラスタ用ネットワークインタフェース","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAにおける差動信号入出力を用いたPCクラスタ用ネットワークインタフェース"},{"subitem_title":"An FPGA Based Network Interface with Differential Signalling I/O for PC Clusters","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高性能アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2003-05-15","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"倉敷芸術科学大学大学院産業科学技術研究科"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Industrial Technology, Kurashiki University of Science and The Arts","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/18581/files/IPSJ-TACS4406011.pdf"},"date":[{"dateType":"Available","dateValue":"2005-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS4406011.pdf","filesize":[{"value":"336.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"36de9e07-88fe-4e9a-8323-5cb18101d7fb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小畑, 正貴"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masaki, Kohata","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGAを利用したネットワークインタフェースの実現と評価について述べる．内部メモリなどのFPGA機能の有効利用と通信プロトコルの単純化により，ホストインタフェースから小規模スイッチまでのすべてのネットワーク機能を1個のFPGAで実現した．リング型PCクラスタを構成して性能評価した結果，100baseT（MPICH，TCP/IP）による通信に対して約3倍の高バンド幅と1/6以下の低レイテンシ性能が得られた．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes the implementation and performance evaluation of an FPGA-based network interface for PC clusters. By using FPGA facilities (such as Block RAM) and a simplified communication protocol, entire network functions including a host interface and a small size switch are implemented on one FPGA chip. Performance evaluations on a ring connected PC cluster, show that this network provides three times the bandwidth and one sixth the latency of a 100baseT (MPICH, TCP/IP) system.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"95","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"87","bibliographicIssueDates":{"bibliographicIssueDate":"2003-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"SIG06(ACS1)","bibliographicVolumeNumber":"44"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:51:16.827178+00:00","id":18581,"links":{}}