{"created":"2025-01-19T00:52:24.038061+00:00","updated":"2025-01-20T03:02:55.204325+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00185204","sets":["1164:2036:7856:9345"]},"path":["9345"],"owner":"11","recid":"185204","title":["MieruSysプロジェクト：複数のFPGAを用いた先進的な計算機システムの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-01-22"},"_buckets":{"deposit":"00730799-0f1f-4ea2-b004-f13e0d5d2dc8"},"_deposit":{"id":"185204","pid":{"type":"depid","value":"185204","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"MieruSysプロジェクト：複数のFPGAを用いた先進的な計算機システムの開発","author_link":["411323","411326","411332","411324","411327","411328","411329","411330","411333","411334","411331","411325"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MieruSysプロジェクト：複数のFPGAを用いた先進的な計算機システムの開発"},{"subitem_title":"MieruSys Project :Developing an Advanced Computer System with Multiple FPGAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA応用システム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-01-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学大学院情報理工学研究科"},{"subitem_text_value":"東京工業大学工学部情報工学科"},{"subitem_text_value":"東京工業大学工学部情報工学科"},{"subitem_text_value":"豊橋技術科学大学電気・電子情報工学系"},{"subitem_text_value":"豊橋技術科学大学電気・電子情報工学系"},{"subitem_text_value":"東京工業大学大学院情報理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/185204/files/IPSJ-SLDM15169037.pdf","label":"IPSJ-SLDM15169037.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM15169037.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"c6fe3d73-1735-4a97-8fd7-13168a407628","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"松田, 裕貴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小川, 愛理"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"味曽野, 智礼"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤枝, 直輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"市川, 周一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉瀬, 謙二"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuki, Matsuda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Eri, Ogawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomohiro, Misono","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoki, Fujieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shuichi, Ichikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kenji, Kise","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，複数の FPGA を用いた将来の計算機システムを開発する MieruSys プロジェクトに関して，その設計と現在の開発状況について述べる．プロセス技術の向上に伴う FPGA の性能向上により，以前は ASIC が用いられた分野においても，FPGA の利用が進んでいる．また，計算機システムに対する利用者の要求は多様化しており，特定アプリケーション向けのアクセラレータはより重要となっている．MieruSys プロジェクトでは，複数の FPGA を用いて計算機の構成要素を設計し，それらをメッシュ接続した計算機システムを開発する．この計算機システムを MieruSys と命名する．メッシュ状のネットワークを採用することで，アクセラレータ等の構成要素を容易に追加でき，性能をスケーラブルに向上させることが期待できる．MieruSys は開発の初期段階であり，現在では Linux と FreeDOS が動作する，1 つの FPGA ボードを用いた MieruSys ver.0.1 の開発が完了している．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes the design and current development of MieruSys project which develops a future computer system with multiple FPGAs. With the performance improvement of FPGA due to scale of process technology, FPGA has become gradually used in the field where ASIC was employed previously. Also, user's de mands for computer systems become diversified and application specific accelerators are becoming needed. In this MieruSys project, we design the computer components with multiple FPGAs, connect them with mesh network, and develop a whole computer system. We name this computer system MieruSys. Using mesh network can allow users to add accelerator components easily, and achieve high scalability. MieruSys is in the early development stage, and currently we have MieruSys ver.0.1 which can run Linux and FreeDOS on an FPGA board.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-01-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"37","bibliographicVolumeNumber":"2015-SLDM-169"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":185204,"links":{}}