{"id":185162,"updated":"2025-01-20T03:03:42.174926+00:00","links":{},"created":"2025-01-19T00:52:21.737333+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00185162","sets":["1164:2036:9343:9344"]},"path":["9344"],"owner":"11","recid":"185162","title":["ネットワーク接続FPGAのためのシリアライゼーションプロトコル高性能化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-01-11"},"_buckets":{"deposit":"27aad4e3-5520-4bda-a6c7-b3973db55477"},"_deposit":{"id":"185162","pid":{"type":"depid","value":"185162","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ネットワーク接続FPGAのためのシリアライゼーションプロトコル高性能化","author_link":["411017","411020","411023","411021","411016","411018","411019","411022","411015","411014"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ネットワーク接続FPGAのためのシリアライゼーションプロトコル高性能化"},{"subitem_title":"Accelerating Serialization Protocols for Network-Attached FPGAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGAシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-01-11","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学理工学部/慶應義塾大学大学院理工学研究科"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/185162/files/IPSJ-SLDM18182024.pdf","label":"IPSJ-SLDM18182024.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM18182024.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"19543d18-3a9d-490a-9f01-d6322a7e3516","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"岩田, 拓真"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三塚, 皐矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中村, 幸平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"徳差, 雄太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 宏紀"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takuma, Iwata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koya, Mitsuzuka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kohei, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuta, Tokusashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroki, Matsutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年,データセンタにおいて増え続けるデータ量と消費電力への対策として,計算負荷の高い処理を FPGA のようなアクセラレータにオフロードするシステムが増えている.FPGA のようなアクセラレータは,一般的に,ホスト CPU とは PCIe を介して接続されるため,複数サーバ間で分散処理を行う場合にホスト CPU を介したサーバ間通信が性能のボトルネックになり得る.そこで,FPGA をネットワークスイッチに直接接続し,ホストを経由せずに複数 FPGA 間で分散処理を行うシステムが登場している.元来,複数サーバ間のデータの通信では,送信データのシリアライゼーション,および,受信データのデシリアライゼーションが行われるが,このようなネットワーク接続 FPGA においては,シリアライゼーションおよびデシリアライゼーションを FPGA 内で行う必要がある.本論文では,10 GbE (10 Gbit Ethernet) ネットワークに直接接続した FPGA を対象に,分散処理で広く使用されている Protocol Buffers および BSON に基づいたシリアライズおよびデシリアライズ機構を設計,実装した.また,高位合成によって作られた任意のアプリケーションロジックをこれらのシリアライズおよびデシリアライズ機構に接続するためのフローを構築した.評価では,これらのシリアライズおよびデシリアライズ機構の性能はソフトウェアよりも最大 45.6 倍改善できることを示し,さらに,ネットワーク接続 FPGA 同士がこれらのシリアライゼーションプロトコルを用いてデータ通信できることを実機で確認した.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術(SLDM)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-01-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"24","bibliographicVolumeNumber":"2018-SLDM-182"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}