{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00185161","sets":["1164:2036:9343:9344"]},"path":["9344"],"owner":"11","recid":"185161","title":["FPGA-NICを用いた逐次学習アルゴリズムOS-ELMの高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-01-11"},"_buckets":{"deposit":"b8740e28-750d-4d96-abd6-90e43848e390"},"_deposit":{"id":"185161","pid":{"type":"depid","value":"185161","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FPGA-NICを用いた逐次学習アルゴリズムOS-ELMの高速化","author_link":["411012","411007","411006","411004","411005","411011","411013","411009","411008","411010"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA-NICを用いた逐次学習アルゴリズムOS-ELMの高速化"},{"subitem_title":"Accelerating Sequential Learning Algorithm OS-ELM using FPGA-NIC","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ニューラルネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-01-11","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学理工学部／慶應義塾大学大学院理工学研究科"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/185161/files/IPSJ-SLDM18182023.pdf","label":"IPSJ-SLDM18182023.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM18182023.pdf","filesize":[{"value":"939.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"5cacac8b-c503-4c8f-94c4-f8b08422b8e0","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"塚田, 峰登"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三塚, 皐矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中村, 幸平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"徳差, 雄太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松谷, 宏紀"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Mineto, Tsukada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koya, Mitsuzuka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kohei, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuta, Tokusashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroki, Matsutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，オートエンコーダーを異常検知に適用する研究が増加している．オートエンコーダーとはニューラルネットワークを用いて入力データを再現するように学習するネットワークであり，教師無しかつ人間による特徴量設計無しで入力データのパターンを捉えることができるのが特徴である．このオートエンコーダーに対し正常データのみを学習させた場合，正常データのパターンとは異なるデータ (異常データ) が入力された時に相対的に損失値が大きくなるため，ここに閾値を設けることで異常を検知できる．しかしながら，勾配計算による通常のニューラルネットを用いたオートエンコーダーでは，即時学習が求められる異常検知問題において，バッチサイズを大きくしなければスループットが出ない．そこで，本論文では近年注目を集める逐次学習アルゴリズム OS-ELM (Online Sequential Extreme Learning Machine) を FPGA に実装し，それがエッジデバイスとして異常検知問題に有効であることを示す．シュミレーションによる評価の結果，CPU 実装の OS-ELM と比較して，学習時のスループットが 3.2 倍から 28.4 倍向上し，また通常のニューラルネットワークによる実装と比較して 2.8 から 323.1 倍向上した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-01-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"23","bibliographicVolumeNumber":"2018-SLDM-182"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":185161,"updated":"2025-01-20T03:03:41.070706+00:00","links":{},"created":"2025-01-19T00:52:21.682675+00:00"}