{"created":"2025-01-19T00:52:21.244121+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00185153","sets":["1164:2036:9343:9344"]},"path":["9344"],"owner":"11","recid":"185153","title":["Javaベース高位合成におけるマルチスレッド機能によるステンシル計算のFPGA実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-01-11"},"_buckets":{"deposit":"38de4b8c-9d0f-4383-9307-81a25f42a49c"},"_deposit":{"id":"185153","pid":{"type":"depid","value":"185153","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Javaベース高位合成におけるマルチスレッド機能によるステンシル計算のFPGA実装","author_link":["410960","410956","410959","410955","410957","410958"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Javaベース高位合成におけるマルチスレッド機能によるステンシル計算のFPGA実装"},{"subitem_title":"FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位設計","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-01-11","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学府情報工学専攻"},{"subitem_text_value":"琉球大学工学部電気電子工学科"},{"subitem_text_value":"東京農工大学工学研究院先端情報科学部門"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/185153/files/IPSJ-SLDM18182015.pdf","label":"IPSJ-SLDM18182015.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM18182015.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2a4d982d-af1c-4075-b591-ba9ab46ad186","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"矢内, 奎太朗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"長名, 保範"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中條, 拓伯"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Keitaro, Yanai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasunori, Osana","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hironori, Nakajo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々は，高位合成を用いたハードウェアアクセラレーションについて，高位合成ツール JavaRock-Thrash を用いて検証を行ってきた．本論文では，JavaRock-Thrash で生成した回路を FPGA の実機上で動作させる際の問題点を検証することを目的として，琉球大で開発されている CPU と FPGA を用いたシステム上にJavaRock-Thrash のマルチスレッドからの並列回路生成機能を用いた回路を組み込んだ．結果として，タイミング制約に課題があった．しかし，正しい結果を出力しているものでは，マルチスレッドを用いた場合に 1 スレッドでは 62 MFLOPS/s に対して 32 スレッドでは 772 MFLOPS/s となり，12 倍高速化した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have been investigating hardware acceleration with an FPGA using Java-based high-level synthesis, JavaRock-Thrash. In this paper, in order to verify circuits generated by JavaRock-Thrash on a commercial FPGA board, we have been trying to design, implement and evaluat acceleration circuits with JavaRock-Thrash using a parallel circuits generation function from multi-threading on a CPU-FPGA Hybrid Cluster Platform Prototype in University of the Ryukyus. As a current result, though there found a problem with timing constraints, in the case of calculation the correct result, our designed circuits performs 772 MFLOPS/s with 32 threads against 62 MFLOPS/s with a single thread, which is about 12 times faster using multi-threading.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-01-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"15","bibliographicVolumeNumber":"2018-SLDM-182"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":185153,"updated":"2025-01-20T03:03:27.896209+00:00","links":{}}