{"created":"2025-01-19T00:52:18.870344+00:00","updated":"2025-01-20T03:03:51.641160+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00185110","sets":["1164:1579:9341:9342"]},"path":["9342"],"owner":"11","recid":"185110","title":["マルチFPGAボードによるRecurrent Neural Networkの高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2018-01-11"},"_buckets":{"deposit":"20cb6e6e-52bf-488b-b742-ad5f749e7146"},"_deposit":{"id":"185110","pid":{"type":"depid","value":"185110","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"マルチFPGAボードによるRecurrent Neural Networkの高速化","author_link":["410695","410690","410692","410694","410689","410688","410691","410693"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチFPGAボードによるRecurrent Neural Networkの高速化"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ニューラルネットワーク","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2018-01-11","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"慶應義塾大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/185110/files/IPSJ-ARC18229001.pdf","label":"IPSJ-ARC18229001.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC18229001.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"f044f33e-b741-478d-b070-1e000542a96b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2018 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山内, 脩吾"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"武者, 千嵯"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"工藤, 知宏"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yugo, Yamauchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazusa, Musha","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomohiro, Kudoh","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"NEDO プロジェクト 「省電力 AI エンジンと異種エンジン統合クラウドによる人工知能プラットフォーム」 では，GPU と FPGA を多数をサーキットスイッチング方式で接続，深層学習，AI アプリケーションのクラウド上での高速化，省電力を目的とする．本稿では仕様が決定し試作機が製造されている FPGA ノード FiC-SW1 を紹介，これを複数用いて Recurrent Neural Network (RNN) の一種 Long Short Term Memory (LSTM) の高速化を検討する．LSTM はここ 2，3 年翻訳や画像説明など高精度な AI モデルに採用され，FPGA でも GPU に競合する計算性能，それを上回る電力性能を達成できる．通信に強い FiC - SW1 ボードの特性を活かし複数 FPGA 上での LSTM 推論高速化を課題とした．複数 FPGA 上の LSTM 推論の実装を，並列化のためのタスク分割，実装，通信，ネットワークの変更によって検討する．評価の結果 9 ノードにおいてマルチ CPU 実装に比べて最大 433 倍，65 ノードの tree トポロジで最大 1907 倍の性能となることがわかった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2018-01-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2018-ARC-229"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":185110,"links":{}}